On Wed, Apr 20, 2022 at 09:14:19AM -0500, joshua stein wrote:
> I noticed in a few dmesgs from Intel 11th gen machines, the L2 cache
> is printed as disabled. Is there some new MSR that needs to be read
> on these CPUs?
l2 cache information is taken from cpuid 0x80000006
Intel documents cpuid eax 0x80000006 in the SDM as
EAX Reserved = 0.
EBX Reserved = 0.
ECX Bits 07 - 00: Cache Line size in bytes.
Bits 11 - 08: Reserved.
Bits 15 - 12: L2 Associativity field *.
Bits 31 - 16: Cache size in 1K units.
EDX Reserved = 0.
* L2 associativity field encodings: 08H - 16 ways
09H - Reserved
00H - Disabled 0AH - 32 ways
01H - 1 way (direct mapped) 0BH - 48 ways
02H - 2 ways 0CH - 64 ways
03H - Reserved 0DH - 96 ways
04H - 4 ways 0EH - 128 ways
05H - Reserved 0FH - Fully associative
06H - 8 ways
07H - See CPUID leaf 04H, sub-leaf 2**
** CPUID leaf 04H provides details of deterministic cache parameters,
including the L2 cache in sub-leaf 2
Do you see 7 for the l2 associativity value?
>
> cpu0 at mainbus0: apid 0 (boot processor)
> cpu0: 11th Gen Intel(R) Core(TM) i5-1135G7 @ 2.40GHz, 4190.34 MHz, 06-8c-01
> cpu0:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,AVX512F,AVX512DQ,RDSEED,ADX,SMAP,AVX512IFMA,CLFLUSHOPT,CLWB,PT,AVX512CD,SHA,AVX512BW,AVX512VL,AVX512VBMI,UMIP,PKU,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu0: 256KB 64b/line disabled L2 cache
> cpu0: smt 0, core 0, package 0
> mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
> cpu0: apic clock running at 38MHz
> cpu0: mwait min=64, max=64, C-substates=0.2.0.1.2.1.1.1, IBE
>
>
