Re: AMD gpu RX 6600 not recognized

[Jonathan Gray]

On Mon, Sep 25, 2023 at 04:22:44PM +0200, Solène Rapenne wrote:
> > Index: sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c,v
> > retrieving revision 1.14
> > diff -u -p -r1.14 amdgpu_ttm.c
> > --- sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c     13 Aug 2023 10:36:26
> > -0000      1.14
> > +++ sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c     21 Sep 2023 08:05:19
> > -0000
> > @@ -1792,6 +1792,7 @@ int amdgpu_ttm_init(struct amdgpu_device
> >         }
> >  
> >         /* Reduce size of CPU-visible VRAM if requested */
> > +amdgpu_vis_vram_limit = 512;
> >         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
> >         if (amdgpu_vis_vram_limit > 0 &&
> >             vis_vram_limit <= adev->gmc.visible_vram_size)
> 
> with this change, the card is recognized correctly without having to
> disable pci bar in the bios

a diff to print some more details

Index: sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c,v
retrieving revision 1.14
diff -u -p -r1.14 amdgpu_ttm.c
--- sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c     13 Aug 2023 10:36:26 -0000      
1.14
+++ sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c     26 Sep 2023 02:13:34 -0000
@@ -1744,6 +1744,54 @@ static int amdgpu_ttm_reserve_tmr(struct
        return 0;
 }
 
+#define PCIE_ECAP_RESIZE_BAR   0x15
+#define RBCAP0                 0x04
+#define RBCTRL0                        0x08
+
+void
+amdgpu_bar_sizes(struct pci_dev *pdev)
+{
+       pcireg_t reg;
+       uint32_t offset, capid;
+       int i, size;
+
+       offset = PCI_PCIE_ECAP;
+       do {
+               reg = pci_conf_read(pdev->pc, pdev->tag, offset);
+               capid = PCI_PCIE_ECAP_ID(reg);
+               if (capid == PCIE_ECAP_RESIZE_BAR)
+                       break;
+               offset = PCI_PCIE_ECAP_NEXT(reg);
+       } while (capid != 0);
+
+       if (capid == 0) {
+               printf("%s: could not find resize bar cap!\n", __func__);
+               return;
+       }
+
+       reg = pci_conf_read(pdev->pc, pdev->tag, offset + RBCAP0);
+       printf("%s: RBCAP0 0x%x sizes: ", __func__, reg);
+       reg = reg >> 4;
+       for (i = 0; i < 24; i++) {
+               size = 1 << i;
+               if (reg & size) {
+                       if (size >= 1024)
+                               printf("%dG ", size >> 10);
+                       else
+                               printf("%dM ", size);
+               }
+       }
+       printf("\n");
+
+       reg = pci_conf_read(pdev->pc, pdev->tag, offset + RBCTRL0);
+       printf("%s: RBCTRL0 0x%x", __func__, reg);
+       size = 1 << ((reg >> 8) & 0x1f);
+       if (size >= 1024)
+               printf(" %dG\n", size >> 10);
+       else
+               printf(" %dM\n", size);
+}
+
 /*
  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
  * gtt/vram related fields.
@@ -1790,6 +1838,18 @@ int amdgpu_ttm_init(struct amdgpu_device
                DRM_ERROR("Failed initializing VRAM heap.\n");
                return r;
        }
+
+#ifdef __OpenBSD__
+       if (amdgpu_vis_vram_limit == 0 && ((adev->flags & AMD_IS_APU) == 0)) {
+               amdgpu_bar_sizes(adev->pdev);
+               printf("GMC real 0x%llx vis 0x%llx,",
+                   adev->gmc.real_vram_size, adev->gmc.visible_vram_size);
+               printf(" FB off 0x%lx size 0x%lx,",
+                   adev->fb_aper_offset, adev->fb_aper_size);
+               printf(" gart size 0x%llx\n", adev->gmc.gart_size);
+               amdgpu_vis_vram_limit = 512;
+       }
+#endif
 
        /* Reduce size of CPU-visible VRAM if requested */
        vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;