01.04.2026 22:52, Alexander Bluhm пишет: > On Wed, Apr 01, 2026 at 06:15:13PM +0200, Kirill A. Korinsky wrote: >> folks, >> >> I think I found the missed piece which brokes my device. >> >> Right now octeon increases ncpus after octciu_intr_establish() is called, >> and kn@ patch moves increases of ncpus into cpuattach() which happens before >> octciu_intr_establish(), so inside that it routes irq into different cpu and >> it somehow affects my setup. >> >> Attached version of the patch removes that routing irq to different cpus >> which actually doesn't work now because ncpus is 1 and % 1 is always 0. >> >> I tested it on my device and it works like a charm. >> >> Feedback? Objection? OK? > > Diff looks good. My machine distributes traffic on loopback over > the 8 softnet threads. Physical interfaces do not distribute traffic > as I have no multiqueue interfaces. > > I am not an octeon expert, but diff looks good to me. Does the > ncpus++ in mips64/cpu.c affect other mips architectures beside > octeon?
I think the octiu(4) diff is missing something; kirill already mailed tech@. loongson has GENERIC.MP, so pretty sure that uses it, too. > > bluhm > > > hw.ncpu=16 > hw.ncpufound=16 > hw.ncpuonline=16 > > [ using 769448 bytes of bsd ELF symbol table ] > Copyright (c) 1982, 1986, 1989, 1991, 1993 > The Regents of the University of California. All rights reserved. > Copyright (c) 1995-2026 OpenBSD. All rights reserved. https://www.OpenBSD.org > > OpenBSD 7.9-beta (GENERIC.MP) #0: Wed Apr 1 21:07:38 CEST 2026 > [email protected]:/usr/src/sys/arch/octeon/compile/GENERIC.MP > real mem = 17179869184 (16384MB) > avail mem = 17003151360 (16215MB) > random: good seed from bootblocks > mainbus0 at root: board 20010 rev 0.20, model cavium,ebb7304 > cpu0 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu0: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu1 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu1: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu2 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu2: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu3 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu3: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu4 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu4: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu5 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu5: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu6 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu6: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu7 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu7: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu8 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu8: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu9 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu9: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu10 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu10: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu11 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu11: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu12 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu12: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu13 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu13: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu14 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu14: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu15 at mainbus0: CN72xx/CN73xx CPU rev 0.2 1800 MHz, CN72xx/CN73xx FPU rev > 0.0 > cpu15: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > clock0 at mainbus0: int 5 > octcrypto0 at mainbus0 > iobus0 at mainbus0 > simplebus0 at iobus0: "soc" > octcit0 at simplebus0 > "bootbus" at simplebus0 not configured > com0 at simplebus0: ns16550a, 64 byte fifo > com0: console > com1 at simplebus0: ns16550a, 64 byte fifo > com1: probed fifo depth: 0 bytes > octgpio0 at simplebus0: 32 pins, xbit 0 > octsmi0 at simplebus0 > octsmi1 at simplebus0 > ogxnexus0 at simplebus0 > ogx0 at ogxnexus0: no phy found > ogx1 at ogxnexus0: no phy found > ogx2 at ogxnexus0: no phy found > ogx3 at ogxnexus0: no phy found > ogxnexus1 at simplebus0 > ogx4 at ogxnexus1: no phy found > ogx5 at ogxnexus1: no phy found > ogx6 at ogxnexus1: no phy found > ogx7 at ogxnexus1: no phy found > ogxnexus2 at simplebus0 > ogx8 at ogxnexus2: SGMII, address f0:9f:c2:c3:21:68 > atphy0 at ogx8 phy 1: AR8035, rev. 4 > "i2c" at simplebus0 not configured > "i2c" at simplebus0 not configured > octmmc0 at simplebus0 > sdmmc0 at octmmc0: 8-bit, mmc high-speed > sdmmc1 at octmmc0: 8-bit, mmc high-speed > "spi" at simplebus0 not configured > octxctl0 at simplebus0: DWC3 rev 0x280a > xhci0 at octxctl0, xHCI 1.0 > usb0 at xhci0: USB revision 3.0 > uhub0 at usb0 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > octxctl1 at simplebus0: DWC3 rev 0x280a > xhci1 at octxctl1, xHCI 1.0 > usb1 at xhci1: USB revision 3.0 > uhub1 at usb1 configuration 1 interface 0 "Generic xHCI root hub" rev > 3.00/1.00 addr 1 > "ocla0" at simplebus0 not configured > "ocla1" at simplebus0 not configured > "ocla2" at simplebus0 not configured > "ocla3" at simplebus0 not configured > "ocla4" at simplebus0 not configured > "vrm0" at simplebus0 not configured > octrng0 at iobus0 base 0x1400000000000 irq 0 > octpcie0 at iobus0: 4 ports > octpcie0 port 0: reset timeout > octpcie0 port 1: reset timeout > octpcie0 port 2: reset timeout > octpcie0 port 3: reset timeout > uhub2 at uhub1 port 1 configuration 1 interface 0 "Genesys Logic USB2.0 Hub" > rev 2.00/88.32 addr 2 > umass0 at uhub2 port 1 configuration 1 interface 0 "Ugreen Ugreen Storage > Device" rev 2.10/1.00 addr 3 > umass0: using SCSI over Bulk-Only > scsibus0 at umass0: 2 targets, initiator 0 > sd0 at scsibus0 targ 1 lun 0: <CT250MX5, 00SSD1, 0> > serial.174c115326A1EE836094 > sd0: 238475MB, 512 bytes/sector, 488397168 sectors > ugen0 at uhub2 port 4 "Atheros Communications product 0x3004" rev 1.10/0.01 > addr 4 > scsibus1 at sdmmc0: 2 targets, initiator 0 > sd1 at scsibus1 targ 1 lun 0: <Sandisk, SEM04G, 0000> removable > sd1: 3776MB, 512 bytes/sector, 7733248 sectors > sdmmc1: can't enable card > vscsi0 at root > scsibus2 at vscsi0: 256 targets > softraid0 at root > scsibus3 at softraid0: 256 targets > root on sd0a (a23a1264f77e0cf5.a) swap on sd0b dump on sd0b > WARNING: CHECK AND RESET THE DATE!
