> Date: Tue, 6 Oct 2026 02:41:54 +0200
> From: Jeremie Courreges-Anglas <[email protected]>
>
> On Tue, Sep 29, 2026 at 02:27:55PM +0200, Jeremie Courreges-Anglas wrote:
> > I'm hitting crashes in bulk builds and weird behavior with code that
> > makes use of the risc-v Vector extension. I'm not sure yet what is
> > going on but since release is approaching I thought I'd share what I
> > have.
>
> I forgot to mention that I get this on my machine at home and the
> ports build cluster, all being k1-based machines.
>
> [...]
> > The location of the crashes appears to vary. From first inspection
> > the kernel code in vector.c looks sane, but I wonder whether sstatus
> > really is correctly managed.
>
> The devil is in the details... here the asm statements were likely
> copied from vector_save() but in vector_load() we really want to
> provide an input operand, not output. The gcc extended asm doc says:
>
> When using ‘=’, do not assume the location contains the existing
> value on entry to the asm, except when the operand is tied to an
> input; ...
>
> The diff below fixes libgcrypt and libjpeg tests for me. I think we
> want this in for release.
>
> ok?
Oops!
ok kettenis@
> Index: vector.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/riscv64/riscv64/vector.c,v
> diff -u -p -r1.1 vector.c
> --- vector.c 9 May 2026 17:38:50 -0000 1.1
> +++ vector.c 6 Oct 2026 00:17:31 -0000
> @@ -157,8 +157,8 @@ vector_load(struct proc *p)
> "r"(&v->v_vdata[24 * riscv_vlenb]) : "memory"
> );
>
> - __asm volatile ("csrw vstart, %0" : "=r"(v->v_vstart));
> - __asm volatile ("csrw vcsr, %0" : "=r"(v->v_vcsr));
> + __asm volatile ("csrw vstart, %0" :: "r"(v->v_vstart));
> + __asm volatile ("csrw vcsr, %0" :: "r"(v->v_vcsr));
>
> vector_disable();
>
>
>
> --
> jca
>
>
