#2782: Cache
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Reporter: ppisa | Owner:
Type: defect | Status: new
Priority: high | Milestone: 4.11
Component: libdl | Version: 4.11
Severity: critical | Keywords:
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Cache manager for ARM and libdl RTL for most of architectures are broken
for 4.11 branch.
The reason is that instruction cache has to be invalidated for most cache
enabled architectures after code modifications because local L1
instruction caches is not included in data cache synchronization
protocols/snooping.
Affected architectures are ARM, probably most of PowerPC, SPARC, MIPS.
Not affected x86 which solve even instruction cache synchronization on
hardware level.
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Ticket URL: <http://devel.rtems.org/ticket/2782>
RTEMS Project <http://www.rtems.org/>
RTEMS Project
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