Kinsey Moore created an issue:
https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5140
Assignee: Kinsey Moore
## Summary
Nested interrupts accidentally use the thread stack when executing instead of
the interrupt stack for that CPU.
>From the ARM Architecture Reference Manual version K.a:
D1.3.2 Exception entry
When an exception is taken to an Exception level, ELx, that is using AArch64
state, all the following occur:
- The contents of PSTATE immediately before the exception was taken is written
to SPSR_ELx.
- The preferred exception return address is written to ELR_ELx.
- The contents of PSTATE immediately after the exception is taken is as
described in rule RWTXBY.
- For synchronous exceptions and SError interrupts, exception syndrome
information is written to ESR_ELx.
- Execution starts from the exception vector at the target Exception level.
When an exception is taken to an Exception level, ELx, that is using AArch64
state, after recording the previous
values in SPSR_ELx, the following PSTATE bits are set:
- PSTATE.EL is set to the target Exception level.
- **All of PSTATE.{D, A, I, F, SP, TCO, PM} are set to 1.**
…
This is currently working due to the fact that any use of the stack by nested
interrupts gets unwound before dispatching occurs.
## Steps to reproduce
Run a workload that generates nested interrupts and verify which stack is being
used for the nested interrupts.
--
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5140
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