Gedare Bloom commented on a discussion on bsps/riscv/shared/mmu/mmu-setup.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1182#note_148165 > + > + return ppn2 | ppn1 | ppn0 | flags; > +} > + > +BSP_START_TEXT_SECTION static inline uint32_t riscv_mmu_get_index( > + uintptr_t address, > + int level > +) > +{ > + uint32_t shift_bits; > + uint32_t mask; > + > + switch (level) { > + case 2: > +#if __riscv_xlen == 32 > + shift_bits = 20; I have to double-check the 32-bit stuff closely. I'll get back to this soon. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1182#note_148165 You're receiving this email because of your account on gitlab.rtems.org.
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