Gedare Bloom created a merge request: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1242
Project:Branches: gedare/rtems:riscv-smode-plic to rtems/rtos/rtems:main Author: Gedare Bloom Assignee: Gedare Bloom ## Summary riscv: enable using PLIC in S-mode The previous addition of s-mode support avoided touching the PLIC registers and only allowed limited use of software interrupts for SMP IPIs. This enables the PLIC in s-mode mapping the registers with the MMU and unifying some aspects of the m-mode and s-mode implementations. Updates #3337 ## Generative AI none <!-- If you have used AI please use the "AI Contribution" template otherwise leave this blank see our fulls statement at https://www.rtems.org/generative-ai/--> <!-- Default settings, if it is a dropdown it will set after submission --> ## Testing ### Summary No test changes in m-mode. The spconsole01.exe goes from failing to passing in s-mode. ### Tests run * Tested with sptests on rv64imafdc w/ and w/o s-mode. * Tested with smptests on rv64imafdc_smp w/ and w/o s-mode. * Tested with sptests rv32imafdc w/ and w/o s-mode. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1242 You're receiving this email because of your account on gitlab.rtems.org.
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