On Thu, 3 Sep 2026 10:08:28 GMT, Gui Cao <[email protected]> wrote:
>> Hi, This PR emits Zalasr load-acquire/store-release instructions (ISA manual
>> Table A.7 mapping) for Java volatile accesses across the interpreter, C1 and
>> C2, guarded by the experimental UseZalasr flag.
>>
>> ### Clarifying the JDK-8358959 concern
>> JDK-8358959[1] stalled on one question: JIT code using the A.7 mapping may
>> interoperate with native code using the old Table A.6 mapping (clang <= 18),
>> and on the seq_cst StoreLoad edge that combination is broken — an A.6 store
>> carries no trailing barrier (it expects the reader to pay) and an A.7 l.aq
>> carries no leading barrier (it expects the writer's .rl annotation), so
>> nobody orders the pair (the ISA manual warns about exactly this pair between
>> the two tables [2]). Since the JVM cannot audit every user JNI library, the
>> issue looked unresolvable.
>>
>> Our key observation: this incompatibility is not introduced by Zalasr — it
>> already exists today. HotSpot's current volatile scheme is "writer pays"
>> (trailing fence w,r on volatile stores, bare volatile loads with no leading
>> fence). An old clang JNI library doing a seq_cst store is "reader pays"
>> (bare store, no trailing barrier). Cross the two and the StoreLoad edge is
>> already unpaid, with no Zalasr instruction involved.
>>
>> This is also exactly why the RISC-V psABI strengthened the C/C++ seq_cst
>> store with a trailing fence (gcc >= 13.3, clang >= 19) and deprecated the
>> old mapping as "must not be combined" (Note 3 of the psABI atomics chapter
>> [3]): the standard already ruled in favor of writer-pays, i.e. HotSpot's
>> side.
>>
>> Consequently, requiring psABI-toolchain-built native code is a pre-existing
>> correctness baseline for the JVM on RISC-V, not a new cost of Zalasr. This
>> PR therefore:
>>
>> 1. gates UseZalasr on the JVM itself being built by a psABI toolchain (gcc
>> >= 13.3 / clang >= 19), so libjvm and the bundled native libraries are
>> guaranteed compatible with the JIT's A.7 code
>> 2. keeps interpreter/C1/C2 volatile accesses mutually compatible (C1
>> volatile loads use l*.aq; interpreter volatile loads gain a leading fence
>> when C2 is active, mirroring the AArch64 JDK-8179954[4] treatment).
>>
>> [1] https://bugs.openjdk.org/browse/JDK-8358959
>> [2] https://docs.riscv.org/reference/isa/v20260120/unpriv/mm-eplan.html
>> [3]
>> https://riscv-non-isa.github.io/riscv-elf-psabi-doc/#_risc_v_atomics_mappings
>> [4] https://bugs.openjdk.org/browse/JDK-8179954
>>
>>
>>
>> ---------
>> - [x] I confirm that I make this contribution in accordance with the
>> [OpenJDK Interim AI Policy...
>
> Gui Cao has updated the pull request incrementally with one additional commit
> since the last revision:
>
> Code format
src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp line 1976:
> 1974: // Volatile stores need no counterpart here:
> BarrierSetC1::store_at_resolved
> 1975: // already brackets them with a leading release fence and a trailing
> full fence.
> 1976: void LIR_Assembler::load_volatile(LIR_Address* from_addr, LIR_Opr dest,
> BasicType type, CodeEmitInfo* info) {
`LIRGenerator::volatile_field_load` and `LIR_Assembler::load_volatile` appear
to be two stages of the same path:
`volatile_field_load` -> `lir_move_volatile` -> `volatile_move_op` ->
`load_volatile`
Would it make sense to keep the `UseZalasr` decision entirely in
`LIR_Assembler::load_volatile`?
`volatile_field_load` could then only emit `volatile_load_mem_reg`, while
`volatile_move_op` would always call `load_volatile` for address-to-register
moves. `load_volatile` could use the current Zalasr implementation when
enabled, and otherwise fall back to:
move_op(src, dest, type, lir_patch_none, info, /* wide */ false);
membar_acquire();
That should preserve the current generated code while keeping the choice
between `load.aq` and `load; fence` in one place in C1. It would also avoid
having the generator depend on how the assembler implements the volatile load.
-------------
PR Review Comment: https://git.openjdk.org/jdk/pull/32309#discussion_r3954092184
