Hi all,

I've "developed" a PFB FIR real optimized for V5, making the (now usual) modification of directly instantiating dsp48s to use the same multipliers and adders. The problem is that this particular optimization requires eliminating the "tap" block in the PFB and doing all the multiplications in the same block. Which makes it incompatible with the drawing architecture of the previous block

I was able to compile an 8-input 1024 channel PFB (w/FFT) at ~286 MHz with no floorplanning, so my guess is that it will be an part of the GBT spectrometer and other high speed spectrometer efforts. Are there any serious objections to me adding a "pfb_fir_real_roach" block? The V2 version can be incorporated eventually.

Sidenote: Can someone tell me how the amount of downshift after the adder tree was derived? It seems excessive in the case I simulated.

Thanks,
-Suraj

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