Hi Henry: Thanks for your great help.
And by the way, I find the Xilinx gateway out block which I drag from the Xilinx blockset can not been identified by the command: gateways_blk_out = find_system(blk, 'FollowLinks','on','LookUnderMasks','all','masktype','Xilinx Gateway Out Block') But the gateway out block in casper library can be idenitfied. I can not see any difference. Do I need to setup something special for the gateway out/in block? Thanks Wan -----Original Message----- From: Henry Chen [mailto:hche...@ssl.berkeley.edu] Sent: Thursday, 27 November 2008 11:57 AM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] The ADC module in ROACH Hi Wanxiang, No such master UCF file exists for any of the boards. All the pinout information is embedded in the BEE2_hw_routes.mat table of the toolflow. The information in this table is read by toolflow functions to extract the pinout information at compile-time based on which yellow blocks you have in your design. The necessary UCF entries are then added to the system.ucf file in XPS_*_base/data during project generation. At this time, the pinout entries for ROACH are incomplete. Thanks, Henry wan.ch...@csiro.au wrote: > Hi: > > Anybody has the full version UCF file of ROACH board? I find only some > pins are located in the UCF file of 10.1 library. > > And where is ADC VHDL code included into top level design? I guess it is > the system.mhs file. But I find the gen_xps_files could not include the > ADC module into system.mhs file for some reason. So can I add ADC block > definition into system.mhs.bac which will be copied into system.mhs, or > this could be done in some parts of gen_xps_files function? > > Thanks > > Wan
