Hi Robert
You are correct, the 10GbEv2 core is preferred for ROACH. It is faster
and has a smaller footprint.
Just yesterday I finished integrating Marc Welz's 10GbE driver and
updated tcpborphserver. This hides all the ARP/MAC address
configuration complexity, so you don't need to worry about the
populating the ARP tables, MAC addresses and IP configurations at the
correct memory offsets. No documentation exists yet. I will upload a
new root filesystem to CASPER SVN this afternoon which bundles all the
necessary code. In the meantime, you can look at http://casper.berkeley.edu/svn/trunk/roach/sw/tgtap/
for the userspace tap driver.
Basically, you start your .bof file on roach as you would on the bee2
(./my_borph_file.bof). This will create the usual /proc/PID/hw/ioreg
entries, one of which will be the 10GbE core with the name as
specified in your simulink design. Then you start the tgtap driver,
which will go off and populate the ARP tables, and continually update
them, so the tables will always be up-to-date, even if your network
changes (like the BEE2 did).
The driver has some simple help in case you forget the arguments:
roach0135:/proc/335/hw/ioreg# tgtap -h
usage: tgtap
-a ip local ip address
-g ip gateway ip address
-m mac MAC address
-p port fabric port
-t name tap device name
-b name borph file name
-T enable test mode (-b specifies normal file)
To run the driver manually (as opposed to configuring it using KATCP),
you can do something like: tgtap -a 10.0.0.129 -m 02:01:02:03:04:06 -p
8888 -b /proc/525/hw/ioreg/gbe0
This will start a new tap network interface device which you can use
as any other normal linux interface, albeit slowly initially (because
the PPC-FPGA interface doesn't run at 10gbs, and DMA is not yet
enabled):
roach0135:/proc/335/hw/ioreg# ifconfig
eth0 Link encap:Ethernet HWaddr 02:00:00:02:01:35
inet addr:192.168.1.35 Bcast:192.168.1.255 Mask:
255.255.255.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:108722 errors:0 dropped:0 overruns:0 frame:0
TX packets:57983 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:22550891 (21.5 MiB) TX bytes:9045336 (8.6 MiB)
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:0 (0.0 b) TX bytes:0 (0.0 b)
tgtap0 Link encap:UNSPEC HWaddr
00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00
inet addr:10.0.0.129 P-t-P:10.0.0.129 Mask:255.255.255.0
UP POINTOPOINT RUNNING NOARP MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:500
RX bytes:0 (0.0 b) TX bytes:0 (0.0 b)
roach0135:/proc/335/hw/ioreg# ping 10.0.0.1
PING 10.0.0.1 (10.0.0.1) 56(84) bytes of data.
64 bytes from 10.0.0.1: icmp_seq=2 ttl=64 time=0.590 ms
64 bytes from 10.0.0.1: icmp_seq=3 ttl=64 time=0.598 ms
Cool, huh?!
It is now also integrated into KATCP, so you can do all the stuff
remotely. See the tap-start and tap-stop commands.
Jason
On 07 Jul 2009, at 11:36, Navarro, Robert wrote:
Hi,
We’re also at JPL working on bringing the first ROACH board we have
received to life. We have already been able to capture some sample
data out of an iADC board connected to a ROACH and would now like to
gain some familiarity with the 10GE ports on the board.
In the BEE_XPS system library, there are two 10GE blocks, the
ten_GbE and the ten_Gbe_v2. For Roach board designs, which block is
preferred. I am guessing the ten_Gbe_v2 block is preferred, but I
wanted to confirm it. Also, I am wondering what documentation is
available for that block. So far, I have found the Wiki page,http://casper.berkeley.edu/wiki/Ten_GbE_v2
, but I was wondering if there is any additional documentation. The
Wiki page mentions some OPB registers: MAC, IP, UDP and ARP. I
generated a test design using the ten_Gbe_v2 (but have not tried
running it yet) and the “core_info.tab” file generated in the
XPS_ROACH_BASE folder did not have any reference to these registers.
Will they appear when I load the BOF file? Also, it mentions in the
Wiki documentation, that some configuration packets may be sent and
received by the microprocessor core. Where would I look to see how
that works?
Thanks,
Robert Navarro
From: [email protected] [mailto:[email protected]
] On Behalf Of Jason Zheng
Sent: Wednesday, July 01, 2009 3:04 PM
To: [email protected]
Subject: [casper] 10GE UDP core
Hi,
This is the first time I'm posting to this mailing list, so allow me
to introduce myself. My name is Jason Zheng, and I am an FPGA design
engineer at JPL. A couple of weeks ago I attended the CASPER
workshop at JPL, and have started to play with the CASPER libraries.
My main interest is to infuse CASPER cores into the instrument
design at JPL.
I've been playing with the 10GE UDP core for a while, and took a
look at the VHDL source code. Comparing the simulink model with the
VHDL source code, I noticed that the simulink model hid the physical
interface (XAUI_XXX) from CASPER users. The simulink model only
shows the internal datapath ports and the LED outputs. It doesn't
seem obvious to me how to run a simulink simulation with the UDP
core fully modeling a computer network. Am I missing some key
information? Or is the UDP core meant to be a black hole/hose only?
cheers,
Jason Zheng
