[casper] Xilinx MAXDELAY constraint compiler bug

[Suraj Gowda]

Hello all,

I've been working on Verilog code that requires the application of a  
MAXDELAY constraint to an 8 bit data bus output from a register  
explicitly forced into the Input/Output Buffer.  When I apply the  
constraint to the whole bus, PAR results show that the Xilinx tools  
attempt to apply a MAXDELAY of 0 ns to bit 6 ONLY, while properly  
applying the MAXDELAY = 2 ns to the other bits.  This result is the  
same over each of the 16 busses to which I have applied this  
constraint.  A workaround I am using right now is to apply the  
constraint to each individual bit, but this prevents me from  
parameterizing the module how I would like to.  Does anybody know  
either (1) how I can use some equivalent of a Verilog generate to make  
sure that the constraint gets applied to each bit of an arbitrary  
width bus, or (2) why the constraint gets misinterpreted?

Thanks,
-Suraj Gowda