Hi!
I am running into trouble with the usr_clk feature on the IBOB.
I brought in a 100MHz 0dBm clock signal through one of the two SMA
connectors on the board ('SMA1'/'SMA2'), set the 'User IP Clock source' to
'usr_clk' and 'GPIO Clock Pin I/O group' to 'iBOB:sma' in the 'XSG core
config' block. After programming the board, the 10/100 Ethernet-related
operations do not work. I am unable to telnet to the board - no ARP
responses are sent back from the IBOB. My UDP data transfer initiation
command - given through the serial interface - freezes the command line. In
this case, in the code, the udp_connect() function call succeeds - the
freeze happens afterwards. (I tried both 'SMA1' and 'SMA2'.)
If I try a different frequency in 'XSG core config' (which is what I really
want), say 10MHz, the EDK/ISE/Bitgen step in BEE XPS fails, giving the
following error message:
ERROR:MDT - Given value for parameter dcm_2:C_CLKIN_PERIOD -
C:\casper_models\counter_db\counter_db\XPS_iBOB_base\system.mhs line 78
(10.000000) is incorrect. The expected value is 100.000000. Please update
the
value in MHS.
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
ERROR:MDT - Error while running "make -f system.make init_bram"
If I manually edit the system.mhs file and change line 78
PARAMETER C_CLKIN_PERIOD = 10.000000
to the suggested expected value (100.000000), the compilation continues,
giving a couple more similar errors, fixing all of which, compilation
succeeds. However, the behaviour of the newly-programmed board remains the
same, giving the same Ethernet problems as described before. Please help!
Also, it would be great if anyone could tell me what the frequency range
supported by usr_clk is.
Thanks!
Jayanth Chennamangalam
