Hi Jonathan, Other specs ?
For SMA 8 or 10 antennas x 2 pols analog input possible For CARMA 15 antennas x 2 pols, or 23 ants x 1 pol, or 23 ants x 2 pols Output sample and accumulation time for cross correlation: typical 10sec, fast for longer baselines 1 sec. Mel. On Thu, Dec 23, 2010 at 1:47 PM, Jonathan Weintroub <jweintr...@cfa.harvard.edu> wrote: > Hi CASPERites, > > Here's a somewhat fluffy RFI which I hope might start a little thought > and/or discussion over the season (acknowledging that not all in the global > collaboration celebrate the traditional Western winter holidays): > > At SMA we are looking into the use of CASPER methods to build a ultra > wideband high spectral resolution correlator. Typical specs are, say, 18 > GHz bandwidth with roughly 300 KHz spectral resolution, by two > polarizations, full Stokes. We are considering using a standard CASPER > packetized FX architecture (FX much better for high res than XF), but in the > relatively unexplored "small number of antennas, wide bandwidth" regime. > If the entire 18 GHz were eaten by one ADC, this would require a sample rate > of 40 Gsps and 64 kpoint PFB. Perhaps more reasonable would be two 9 GHz > BW blocks and a 32 k PFB sampled at about 20 Gsps, or three 6 GHz / 16 or 32 > k PFB / 14 Gsps. > > To start we are looking closely at the FPGA resource utilization of large > PFBs. Something that probably is common knowledge amongst those experienced > in FX correlator design is that the demux factor drives the utilization much > faster than the size of the PFB. In that sense bandwidth is far more > expensive than spectral resolution. We've put some effort into accurately > quantifying the utilization, at least as far as multipliers and adders are > concerned, and are expanding this analysis to block ram and other resources. > And demux factor is typically radix 2, so it is very much quantized. > > For example at 20 Gsps one might consider a demux factor of 128 resulting in > an FPGA clock rate of 156 MHz, which is quite comfortable for the FPGA. > Alternatively a demux factor of 64 with corresponding FPGA clock of twice > that, or over 300 MHz. Traditionally a rather uncomfortable regime for > CASPER (we're unusual, I believe, in running iBOBs at 256 MHz for the VLBI > phased array). The trouble is our analysis shows that the difference > between these two demux setting in the size of PFB one can fit in a Virtex 6 > is really quite large, and 128 definitely won't allow us to do what we need > to do. > > So we are increasingly highly motivated to run the FPGAs faster still. Just > a 20% increment from the 256 MHz which we currently view as a practical > upper limit allows us to cross a clock rate threshold which then enables a > factor of two decrease in demux factor, and consequent even larger increment > in the realizable PFB size. > > Which is just a long winded way of asking if there are any others in the > collaboration motivated to run the FPGAs faster, and whether any tricks can > be shared? In particular, does the CASPER toolflow support multiple clock > domains? Our understanding is not yet, but that's based on incomplete > information. We know that there exists Virtex 5 (?) IP FFT cores which > supposably run at greater than 500 MHz rates, using the enhanced > interconnect between DSP slices. > > While on this topic of high demux factors, the tool flow largely chokes on > demux factors of 32 or greater. Any tips here would also be appreciated. > > If anyone can cast light on this general topic and related concerns it would > be very much appreciated. > > Jonathan Weintroub > SAO > > > > >
