Hello,
I've been trying to get matlab to compile the first
turorial...or really to compile anything for that matter...i wasn't able to
find any solutions online...bee_xps gave the following output. any ideas on
what this could be?
#----------------------------------------------#
# Starting program par
# par -ise ../__xps/ise/system.ise -xe n -w -ol high system_map.ncd
system.ncd
system.pcf
#----------------------------------------------#
Release 11.3 - par L.57 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/data/parBmgr.acd>
with local file
</opt/Xilinx/11.1/ISE/data/parBmgr.acd>
Loading device for application Rf_Device from file '5vsx95t.nph' in
environment
/opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK.
"system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed
-1
Constraints file: system.pcf.
"system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed
-1
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to
85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.66 2009-08-24".
Device Utilization Summary:
Number of BUFGs 3 out of 32 9%
Number of DCM_ADVs 2 out of 12 16%
Number of ILOGICs 37 out of 800 4%
Number of External IOBs 45 out of 640 7%
Number of LOCed IOBs 45 out of 45 100%
Number of OLOGICs 18 out of 800 2%
Number of Slice Registers 265 out of 58880 1%
Number used as Flip Flops 265
Number used as Latches 0
Number used as LatchThrus 0
Number of Slice LUTS 401 out of 58880 1%
Number of Slice LUT-Flip Flop pairs 424 out of 58880 1%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
WARNING:Par:288 - The signal infrastructure_inst/dly_clk has no load. PAR
will not attempt to route this signal.
WARNING:Par:288 - The signal sys_reset has no load. PAR will not attempt to
route this signal.
Starting Router
Phase 1 : 1807 unrouted; REAL time: 14 secs
Phase 2 : 1443 unrouted; REAL time: 14 secs
Phase 3 : 521 unrouted; REAL time: 15 secs
Phase 4 : 521 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 21 secs
Total REAL time to Router completion: 21 secs
Total CPU time to Router completion: 21 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max
Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk |BUFGCTRL_X0Y31| No | 27 | 0.696 |
2.335 |
+---------------------+--------------+------+------+------------+-------------+
| epb_clk | BUFGCTRL_X0Y0| No | 113 | 0.777 |
2.319 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case |
Best Case | Timing | Timing
| | Slack |
Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" | MINPERIOD | 1.668ns|
8.332ns| 0| 0
100 MHz HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
NET "epb_cs_n_IBUF" MAXDELAY = 4 ns | MAXDELAY | 2.306ns|
1.694ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_epb_clk = PERIOD TIMEGRP "epb_clk" 88 | SETUP | 3.453ns|
7.262ns| 0| 0
MHz HIGH 50% | HOLD |
0.420ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_infrastructure_inst_infrastructure_ins | SETUP | 7.536ns|
2.464ns| 0| 0
t_sys_clk_dcm = PERIOD TIMEGRP "i | HOLD |
0.494ns| | 0| 0
nfrastructure_inst_infrastructure_inst_sy | |
| | |
s_clk_dcm" TS_sys_clk_n HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_sys_clk_n
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period
| Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative
| Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_n | 10.000ns| 8.332ns|
2.464ns| 0| 0| 0| 1005|
| TS_infrastructure_inst_infrast| 10.000ns| 2.464ns|
N/A| 0| 0| 1005| 0|
| ructure_inst_sys_clk_dcm | | |
| | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
*** glibc detected *** /opt/Xilinx/11.1/ISE/bin/lin/unwrapped/par: double
free or corruption (!prev): 0x09725e98 ***
======= Backtrace: =========
/lib/libc.so.6[0x5336c5]
/lib/libc.so.6(cfree+0x59)[0x533b09]
/opt/Xilinx/11.1/ISE/lib/lin/libstlport.so.5.1(_ZdlPv+0x21)[0xe9d211]
/opt/Xilinx/11.1/ISE/lib/lin/libxalanc.so(_ZN11xalanc_1_1014XSLTEngineImpl9terminateEv+0x273)[0x26bfcb3]
/opt/Xilinx/11.1/ISE/lib/lin/libxalanc.so(_ZN11xalanc_1_108XSLTInitD1Ev+0x24)[0x26c8844]
/opt/Xilinx/11.1/ISE/lib/lin/libxalanc.so(_ZN11xalanc_1_1016XalanTransformer9terminateEv+0x49)[0x2765219]
/opt/Xilinx/11.1/ISE/lib/lin/libTw.so[0x213533a]
/opt/Xilinx/11.1/ISE/lib/lin/libTw.so[0x207ddf0]
/opt/Xilinx/11.1/ISE/lib/lin/libTw.so[0x220fd9a]
/lib/ld-linux.so.2[0x640996]
/lib/libc.so.6(exit+0xe9)[0x4f5ec9]
/lib/libc.so.6(__libc_start_main+0xe4)[0x4dfea4]
/opt/Xilinx/11.1/ISE/bin/lin/unwrapped/par(__gxx_personality_v0+0x185)[0x8049451]
======= Memory map: ========
00110000-00257000 r-xp 00000000 fd:00 99523396
/opt/Xilinx/11.1/ISE/lib/lin/libPortability.so
00257000-00258000 rw-p 00147000 fd:00 99523396
/opt/Xilinx/11.1/ISE/lib/lin/libPortability.so
00258000-00302000 r-xp 00000000 fd:00 99523440
/opt/Xilinx/11.1/ISE/lib/lin/libtcl8.4.so
00302000-00308000 rw-p 000aa000 fd:00 99523440
/opt/Xilinx/11.1/ISE/lib/lin/libtcl8.4.so
00308000-0038b000 r-xp 00000000 fd:00 99523478
/opt/Xilinx/11.1/ISE/lib/lin/libboost_regex-gcc-p-1_33_1.so.1.33.1
0038b000-0038d000 rw-p 00083000 fd:00 99523478
/opt/Xilinx/11.1/ISE/lib/lin/libboost_regex-gcc-p-1_33_1.so.1.33.1
0038d000-003b3000 r-xp 00000000 fd:00 99523642
/opt/Xilinx/11.1/ISE/lib/lin/libboost_iostreams-gcc-p-1_33_1.so.1.33.1
003b3000-003b5000 rw-p 00026000 fd:00 99523642
/opt/Xilinx/11.1/ISE/lib/lin/libboost_iostreams-gcc-p-1_33_1.so.1.33.1
003b5000-00436000 r-xp 00000000 fd:00 99523480
/opt/Xilinx/11.1/ISE/lib/lin/libisl_iostreams.so
00436000-00437000 rw-p 00080000 fd:00 99523480
/opt/Xilinx/11.1/ISE/lib/lin/libisl_iostreams.so
00437000-00441000 r-xp 00000000 fd:00 13992527
/usr/local/matlab/sys/os/glnx86/libgcc_s.so.1
00441000-00442000 rw-p 00009000 fd:00 13992527
/usr/local/matlab/sys/os/glnx86/libgcc_s.so.1
00442000-00449000 r-xp 00000000 fd:00 58261555 /lib/librt-2.5.so
00449000-0044a000 r--p 00007000 fd:00 58261555 /lib/librt-2.5.so
0044a000-0044b000 rw-p 00008000 fd:00 58261555 /lib/librt-2.5.so
0044b000-00460000 r-xp 00000000 fd:00 99523738
/opt/Xilinx/11.1/ISE/lib/lin/libUtilC_QualityData.so
00460000-00461000 rw-p 00014000 fd:00 99523738
/opt/Xilinx/11.1/ISE/lib/lin/libUtilC_QualityData.so
00461000-00465000 r-xp 00000000 fd:00 99523908
/opt/Xilinx/11.1/ISE/lib/lin/libGenParTask.so
00465000-00466000 rw-p 00003000 fd:00 99523908
/opt/Xilinx/11.1/ISE/lib/lin/libGenParTask.so
00466000-004b3000 r-xp 00000000 fd:00 99523550
/opt/Xilinx/11.1/ISE/lib/lin/libUtilities.so
004b3000-004b4000 rw-p 0004c000 fd:00 99523550
/opt/Xilinx/11.1/ISE/lib/lin/libUtilities.so
004b4000-004b5000 r-xp 00000000 fd:00 99523936
/opt/Xilinx/11.1/ISE/lib/lin/libCit_Core.so
004b5000-004b6000 rw-p 00000000 fd:00 99523936
/opt/Xilinx/11.1/ISE/lib/lin/libCit_Core.so
004b6000-004b9000 r-xp 00000000 fd:00 99523917
/opt/Xilinx/11.1/ISE/lib/lin/libSec_Urev.so
004b9000-004ba000 rw-p 00002000 fd:00 99523917
/opt/Xilinx/11.1/ISE/lib/lin/libSec_Urev.so
004ba000-004c7000 r-xp 00000000 fd:00 99523807
/opt/Xilinx/11.1/ISE/lib/lin/libRf_HelperBase.so
004c7000-004c8000 rw-p 0000c000 fd:00 99523807
/opt/Xilinx/11.1/ISE/lib/lin/libRf_HelperBase.so
004c8000-004c9000 r-xp 00000000 fd:00 99523938
/opt/Xilinx/11.1/ISE/lib/lin/libTcl_Tcl.so
004c9000-004ca000 rw-p 00000000 fd:00 99523938
/opt/Xilinx/11.1/ISE/lib/lin/libTcl_Tcl.so
004ca000-0061d000 r-xp 00000000 fd:00 58261527 /lib/libc-2.5.so
0061d000-0061f000 r--p 00153000 fd:00 58261527 /lib/libc-2.5.so
0061f000-00620000 rw-p 00155000 fd:00 58261527 /lib/libc-2.5.so
00620000-00623000 rw-p 00620000 00:00 0
00623000-00631000 r-xp 00000000 fd:00 99523794
/opt/Xilinx/11.1/ISE/lib/lin/libXdh_Shape.so
00631000-00632000 rw-p 0000e000 fd:00 99523794
/opt/Xilinx/11.1/ISE/lib/lin/libXdh_Shape.so
00632000-0064d000 r-xp 00000000 fd:00 58261519 /lib/ld-2.5.so
0064d000-0064e000 r--p 0001a000 fd:00 58261519 /lib/ld-2.5.so
0064e000-0064f000 rw-p 0001b000 fd:00 58261519 /lib/ld-2.5.so
0064f000-006e8000 r-xp 00000000 fd:00
All signals are completely routed.
WARNING:Par:283 - There are 2 loadless signals in this design. This design
will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 25 secs
Total CPU time to PAR completion: 24 secs
Peak Memory Usage: 321 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0
Writing design to file system.ncd
PAR done!
ERROR:Xflow - par: application received signal 6.
ERROR:Xflow:42 - Aborting flow execution...
gmake: *** [__xps/system_routed] Error 1
ERROR:EDK - Error while running "gmake -f system.make bits".
Return code = 2
No changes to be saved in MSS file
Saved project XMP file
cp: cannot stat `implementation/system.bit': No such file or directory
bit file open failed
chmod: cannot access `implementation/system.bof': No such file or directory
cp: cannot stat `implementation/system.bof': No such file or directory
Error using ==> gen_xps_files at 689
Programation files generation failed, EDK compilation probably also failed.
--
-- Louis Dartez
(956) 372-5812
Arecibo Remote Command Center Scholar
Center for Gravitational Wave Astronomy
University of Texas at Brownsville
