Hi Casperites,
I have a new ADC board (6 channels, 12-bits, 1GSPS) for which I wrote a
yellow block. I have the usual option of clocking the FPGA from the
sysclk or from the ADC clock, and both options work fine. But when you
clock the whole thing from the ADC clock, you get into the following
situation: there's a reset input to the yellowblock, which resets a DCM
which provides clocks to the ISERDES modules, and also drives a second
DCM to provide the four phases of clock to the FPGA fabric. So, I
connect this reset to a software register so that I can reset the DCM
if, say, the sampling clock has been removed. But when I assert the
reset, the whole FPGA stops, and I can not de-assert the reset, so the
whole thing freezes until I reconfigure the FPGA. I gather that the
software registers are resynch'ed to the fabric clock; is there a way to
defeat this resynching, or some other option for switching clocks? It'd
be trivial in Verilog, but I don't see how to do it in Simulink.
Thanks for any help,
Rick Raffanti
