Re: [casper] roach & adc sampling rate

[Louis Dartez]

Hello Andrew,

                Thank you for answering my questions. This has helped 
me clear up a few doubts I had concerning a design I'm working with.

-- Louis Dartez
(956) 372-5812
Arecibo Remote Command Center Scholar
Center for Advanced Radio Astronomy
University of Texas at Brownsville


On 1/25/12 1:42 AM, Andrew Martens wrote:
Hi Louis

                     Why is it that I had to go in change these
parameters? Why isn't this available from Simulink, for example?
It should be transparent to the user. No-one has had the time (or need)
to make the change thus far.

                     Is this usually the fix that other people will
incorporate when they need to work with lower sampling rates? Or do
most people just downsample?
Either;
very few people work at low sampling rates;
Or;
people have figured out the changes needed and that has not fed back
into the toolflow (yet?)

                      Does changing the DCM values from "HIGH" to "LOW"
have any other consequences that could come back and bite me? What are
the ranges of frequencies that "HIGH"&  "LOW" refer to?
The settings only affect the frequencies the DCM is tuned to work at
(possible input and output frequencies). These are described in the
Virtex 5 data sheet (ds202.pdf). The effects of a 'LOW' or 'HIGH'
setting depend on how you are using a DCM (e.g which outputs are used)
and the data sheet should be consulted. In this case 'LOW' allows an
input clock frequency (on CLKIN) between 32MHz and 120MHz, and 'HIGH'
between 120MHz and 450MHz.

                     Would one of the reasons to downsample instead of
changing the clock rate be that the Virtex5 (which is what I'm using)
works better at 200MHz? What is the Virtex5's optimal clock rate?

We try to optimise efficiency when using an FPGA as FPGA processing
resources are expensive. This means using few resources at a high clock
rate. We find that we can get most designs to run at an FPGA clock rate
of around 200MHz on a ROACH (there is currently a big push to increase
this). We thus maximise efficiency (and minimise hardware costs) by
aiming at ADC sampling rates that translate back to this FPGA clock
rate.

Regards
Andrew