> With ADCs in the design, I can use the adcX_clk, while I want to use a clock > a little higher than adcX_clk to process with the data. How can I deal with > the second clock? The short answer is that you can't. Simulink can create a fake 2x clock for you by adding enable/clock gating lines to all your other logic and clocking the entire physical device at twice the speed but this rarely works unless you're wanting to run everything very slowly. In all cases, the Simulink domain is always clocked by one clock domain.
This multi-clock region requirement came through quite strongly at the last CASPER workshop and is something we're thinking about, especially in light of overlapping PFB requirements. It's a tricky thing though. FWIW, Matlab's HDL coder can apparently support such things, and looks like a promising alternative to XSG in many other ways too. It's also something that's being built into the new MyHDL toolflow from the start. But these new 'flows are all a long way away if they ever get off the ground. The current CASPER toolflow is designed so that all the DSP operations happen synchronously with the input data. This locally-syncronous model is actually rather efficient and is in general a good one to follow. I'd suggest you try'n tweak your processing logic to support synchronous data. In terms of 10GbE cores and other peripherals requiring additional clock domains (such as the bus infrastructure), this is handled automatically in the toolflow by the base system, coded in HDL (see the XPS infrastructure/pcores directory for the hairy details). In general, you don't have to worry about this stuff. Jason
