Yes, there are a couple of counters and delays On Fri, Jan 11, 2013 at 12:19 PM, G Jones <glenn.calt...@gmail.com> wrote:
> Just a wild guess (I haven't looked at the model file)... do you have > any register/delay/counter in your design? You need at least one > xilinx block in your simulink diagram that requires a clock otherwise > the synthesis will strip out your simulink clock and the design won't > compile. > > On Fri, Jan 11, 2013 at 12:13 PM, Ioana Alexandra Zelko > <ioana.ze...@gmail.com> wrote: > > Hello, thank you so much for your help! > > > > This is one of the files I tried to compile. > > There is only one_GbE yellow block, no ten_GbE yellow block. > > > > The version of the mlib_devel is as it was at Dec 12, 2012. > > Or rather, when I do " git show" the last commit is listed from then. > > (commit 81a1750ef83c86727a0ed2d1c23582e4868f4a80) > > > > The clock was set to sys_clk, at 201 MHz > > > > I looked at platgen.log, and as David said, there was an errror listed > > above, sending me to look at system.mhs. > > > > Here is platgen.log, and then the system.mhs: > > > > > ................................................................................................ > > > > Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd > > (lin64) > > Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. > > > > Command Line: platgen -p xc6vsx475tff1759-1 -lang vhdl -intstyle default > > -msg > > __xps/ise/xmsgprops.lst system.mhs > > > > Parse > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs ... > > > > Read MPD definitions ... > > > > Overriding IP level properties ... > > > > Computing clock values... > > INFO:EDK:740 - Cannot determine the input clock associated with port : > > infrastructure_inst:epb_clk. Clock DRCs will not be performed on this > > core > > and cores connected to it. > > INFO:EDK:740 - Cannot determine the input clock associated with port : > > infrastructure_inst:epb_clk. Clock DRCs will not be performed on this > > core > > and cores connected to it. > > INFO:EDK:740 - Cannot determine the input clock associated with port : > > infrastructure_inst:epb_clk. Clock DRCs will not be performed on this > > core > > and cores connected to it. > > INFO:EDK:740 - Cannot determine the input clock associated with port : > > infrastructure_inst:epb_clk. Clock DRCs will not be performed on this > > core > > and cores connected to it. > > > > Performing IP level DRCs on properties... > > > > Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC... > > INFO:EDK:4130 - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding > > PARAMETER > > C_NUM_MASTERS value to 1 - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/pcores/opb_v20_v1_10_c/data/opb_v20_v2_1_0.mpd line 74 > > INFO:EDK:4130 - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding > > PARAMETER > > C_NUM_SLAVES value to 2 - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/pcores/opb_v20_v1_10_c/data/opb_v20_v2_1_0.mpd line 75 > > > > Checking platform address map ... > > > > Checking platform configuration ... > > IPNAME: opb_v20, INSTANCE: opb0 - 1 master(s) : 2 slave(s) > > > > Checking port drivers... > > WARNING:EDK:4181 - PORT: sys_clk90, CONNECTOR: sys_clk90 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 89 > > WARNING:EDK:4181 - PORT: sys_clk180, CONNECTOR: sys_clk180 - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 90 > > WARNING:EDK:4181 - PORT: sys_clk270, CONNECTOR: sys_clk270 - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 91 > > WARNING:EDK:4181 - PORT: sys_clk_lock, CONNECTOR: sys_clk_lock - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 92 > > WARNING:EDK:4181 - PORT: sys_clk2x, CONNECTOR: sys_clk2x - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 93 > > WARNING:EDK:4181 - PORT: sys_clk2x90, CONNECTOR: sys_clk2x90 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 94 > > WARNING:EDK:4181 - PORT: sys_clk2x180, CONNECTOR: sys_clk2x180 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 95 > > WARNING:EDK:4181 - PORT: sys_clk2x270, CONNECTOR: sys_clk2x270 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 96 > > WARNING:EDK:4181 - PORT: aux_clk, CONNECTOR: aux_clk - floating > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 97 > > WARNING:EDK:4181 - PORT: aux_clk90, CONNECTOR: aux_clk90 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 98 > > WARNING:EDK:4181 - PORT: aux_clk180, CONNECTOR: aux_clk180 - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 99 > > WARNING:EDK:4181 - PORT: aux_clk270, CONNECTOR: aux_clk270 - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 100 > > WARNING:EDK:4181 - PORT: aux_clk2x, CONNECTOR: aux_clk2x - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 101 > > WARNING:EDK:4181 - PORT: aux_clk2x90, CONNECTOR: aux_clk2x90 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 102 > > WARNING:EDK:4181 - PORT: aux_clk2x180, CONNECTOR: aux_clk2x180 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 103 > > WARNING:EDK:4181 - PORT: aux_clk2x270, CONNECTOR: aux_clk2x270 - floating > > connection - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 104 > > WARNING:EDK:4181 - PORT: idelay_rdy, CONNECTOR: idelay_rdy - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 107 > > WARNING:EDK:4181 - PORT: soft_reset, CONNECTOR: soft_reset - floating > > connection > > - > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/system.mhs line 168 > > > > Performing Clock DRCs... > > > > Performing Reset DRCs... > > > > Overriding system level properties... > > > > Running system level update procedures... > > > > Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC... > > > > Running system level DRCs... > > > > Performing System level DRCs on properties... > > > > Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC... > > > > Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC... > > > > Modify defaults ... > > > > Creating stub ... > > > > Processing licensed instances ... > > Completion time: 0.00 seconds > > > > Creating hardware output directories ... > > > > Managing hardware (BBD-specified) netlist files ... > > IPNAME:small_test INSTANCE:small_test_xsg_core_config - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 181 - Copying (BBD-specified) netlist files. > > IPNAME:temac INSTANCE:temac_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 37 - Copying (BBD-specified) netlist files. > > IPNAME:gbe_udp INSTANCE:small_test_one_gbe - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 214 - Copying (BBD-specified) netlist files. > > > > Managing cache ... > > > > Elaborating instances ... > > > > Writing HDL for elaborated instances ... > > > > Inserting wrapper level ... > > Completion time: 0.00 seconds > > > > Constructing platform-level connectivity ... > > Completion time: 0.00 seconds > > > > Writing (top-level) BMM ... > > > > Writing (top-level and wrappers) HDL ... > > > > Generating synthesis project file ... > > > > Running XST synthesis ... > > > > INFO:EDK:4211 - The following instances are synthesized with XST. The MPD > > option > > IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST > > synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. > > INSTANCE:temac_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 37 - Running XST synthesis > > INSTANCE:sgmii_phy_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 48 - Running XST synthesis > > INSTANCE:infrastructure_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 70 - Running XST synthesis > > INSTANCE:reset_block_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 111 - Running XST synthesis > > INSTANCE:opb0 - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 121 - Running XST synthesis > > INSTANCE:epb_opb_bridge_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 130 - Running XST synthesis > > INSTANCE:epb_infrastructure_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 147 - Running XST synthesis > > INSTANCE:sys_block_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 156 - Running XST synthesis > > INSTANCE:small_test_xsg_core_config - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 181 - Running XST synthesis > > INSTANCE:small_test_one_gbe - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 214 - Running XST synthesis > > ERROR:EDK:546 - Aborting XST flow execution! > > INFO:EDK:2246 - Refer to > > > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2 > > _base/synthesis/system_small_test_one_gbe_wrapper_xst.srp for details > > > > Running NGCBUILD ... > > IPNAME:system_temac_inst_wrapper INSTANCE:temac_inst - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 37 - Running NGCBUILD > > IPNAME:system_small_test_xsg_core_config_wrapper > > INSTANCE:small_test_xsg_core_config - > > > /home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_ba > > se/system.mhs line 181 - Running NGCBUILD > > > > INFO:EDK:3509 - NCF files should not be modified as they will be > > regenerated. > > If any constraint needs to be overridden, this should be done by > > modifying > > the data/system.ucf file. > > > > Rebuilding cache ... > > ERROR:EDK:440 - platgen failed with errors! > > > > > ........................................................................................................................ > > > > And now system.mhs > > > > > > > ........................................................................................................................ > > > > # > > > ############################################################################## > > # Target Board: ROACH v2.0 > > # Family: virtex6 > > # Device: xc6vsx475t > > # Package: ff1759 > > # Speed Grade: -1 > > # Processor: None > > # System clock frequency: 100.000000 MHz > > # > > > ############################################################################## > > > > PARAMETER VERSION = 2.1.0 > > > > > > # Clock Ports > > PORT sys_clk_n = sys_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 > > PORT sys_clk_p = sys_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 > > #PORT aux_clk_n = aux_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 > > #PORT aux_clk_p = aux_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 > > PORT aux_clk_n = aux_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 201000000 > > PORT aux_clk_p = aux_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 201000000 > > # PORT aux_synci_n = aux_synci_n, DIR = I, SIGIS = CLK, CLK_FREQ = > > 200000000 > > # PORT aux_synci_p = aux_synci_p, DIR = I, SIGIS = CLK, CLK_FREQ = > > 200000000 > > # PORT aux_synco_n = aux_synco_n, DIR = I, SIGIS = CLK, CLK_FREQ = > > 200000000 > > # PORT aux_synco_p = aux_synco_p, DIR = I, SIGIS = CLK, CLK_FREQ = > > 200000000 > > # EPB Ports > > PORT epb_clk_in = epb_clk_in, DIR = I > > PORT epb_data = epb_data, DIR = IO, VEC = [0:31] > > PORT epb_addr = epb_addr, DIR = I, VEC = [5:29] > > PORT epb_cs_n = epb_cs_n, DIR = I > > PORT epb_be_n = epb_be_n, DIR = I, VEC = [0:3] > > PORT epb_r_w_n = epb_r_w_n, DIR = I > > PORT epb_oe_n = epb_oe_n, DIR = I > > PORT epb_doe_n = epb_doe_n, DIR = O > > PORT epb_rdy = epb_rdy, DIR = O > > PORT ppc_irq_n = ppc_irq_n, DIR = O > > > > BEGIN temac > > PARAMETER INSTANCE = temac_inst > > PARAMETER HW_VER = 1.00.a > > PARAMETER REG_SGMII = 1 > > PARAMETER PHY_ADR = 0 > > PORT clk_125 = clk_125 > > PORT reset = sys_reset > > BUS_INTERFACE SGMII = sgmii > > BUS_INTERFACE MAC = mac > > END > > > > BEGIN sgmii_phy > > PARAMETER INSTANCE = sgmii_phy_inst > > PARAMETER HW_VER = 1.00.a > > PORT mgt_rx_n = sgmii_rx_n_i > > PORT mgt_rx_p = sgmii_rx_p_i > > PORT mgt_tx_n = sgmii_tx_n_i > > PORT mgt_tx_p = sgmii_tx_p_i > > PORT mgt_clk_n = sgmii_clkref_n_i > > PORT mgt_clk_p = sgmii_clkref_p_i > > PORT mgt_reset = sys_reset > > PORT clk_125 = clk_125 > > BUS_INTERFACE SGMII = sgmii > > END > > > > # MARVELL PHY SGMII Pins > > PORT sgmii_rx_n = sgmii_rx_n_i, DIR = I > > PORT sgmii_rx_p = sgmii_rx_p_i, DIR = I > > PORT sgmii_tx_n = sgmii_tx_n_i, DIR = O > > PORT sgmii_tx_p = sgmii_tx_p_i, DIR = O > > PORT sgmii_clkref_n = sgmii_clkref_n_i, DIR = I > > PORT sgmii_clkref_p = sgmii_clkref_p_i, DIR = I > > > > BEGIN roach_infrastructure > > PARAMETER INSTANCE = infrastructure_inst > > PARAMETER HW_VER = 1.00.a > > PARAMETER CLK_FREQ = 201 > > PARAMETER CLK_HIGH_LOW = low > > PARAMETER MULTIPLY = 8 > > PARAMETER DIVIDE = 4 > > PARAMETER DIVCLK = 1 > > #PARAMETER CLK_FREQ = 100 > > PORT sys_clk_n = sys_clk_n > > PORT sys_clk_p = sys_clk_p > > PORT aux_clk_n = aux_clk_n > > PORT aux_clk_p = aux_clk_p > > # PORT aux_synci_n = aux1_clk_n > > # PORT aux_synci_p = aux1_clk_p > > # PORT aux_synco_n = aux1_clk_n > > # PORT aux_synco_p = aux1_clk_p > > PORT epb_clk_in = epb_clk_in > > PORT sys_clk = sys_clk > > PORT sys_clk90 = sys_clk90 > > PORT sys_clk180 = sys_clk180 > > PORT sys_clk270 = sys_clk270 > > PORT sys_clk_lock = sys_clk_lock > > PORT sys_clk2x = sys_clk2x > > PORT sys_clk2x90 = sys_clk2x90 > > PORT sys_clk2x180 = sys_clk2x180 > > PORT sys_clk2x270 = sys_clk2x270 > > PORT aux_clk = aux_clk > > PORT aux_clk90 = aux_clk90 > > PORT aux_clk180 = aux_clk180 > > PORT aux_clk270 = aux_clk270 > > PORT aux_clk2x = aux_clk2x > > PORT aux_clk2x90 = aux_clk2x90 > > PORT aux_clk2x180 = aux_clk2x180 > > PORT aux_clk2x270 = aux_clk2x270 > > PORT epb_clk = epb_clk > > PORT idelay_rst = power_on_rst > > PORT idelay_rdy = idelay_rdy > > PORT op_power_on_rst = power_on_rst > > END > > > > BEGIN reset_block > > PARAMETER INSTANCE = reset_block_inst > > PARAMETER HW_VER = 1.00.a > > PARAMETER WIDTH = 1000 > > PORT clk = sys_clk > > PORT ip_async_reset_i = power_on_rst > > PORT ip_reset_i = power_on_rst > > PORT op_reset_o = sys_reset > > END > > > > BEGIN opb_v20 > > PARAMETER INSTANCE = opb0 > > PARAMETER HW_VER = 1.10.c > > PARAMETER C_EXT_RESET_HIGH = 1 > > PARAMETER C_REG_GRANTS = 0 > > PORT SYS_Rst = power_on_rst > > PORT OPB_Clk = epb_clk > > END > > > > BEGIN epb32_opb_bridge > > PARAMETER INSTANCE = epb_opb_bridge_inst > > PARAMETER HW_VER = 1.00.a > > BUS_INTERFACE MOPB = opb0 > > PORT epb_clk = epb_clk > > PORT epb_cs_n = epb_cs_n > > PORT epb_oe_n = epb_oe_n > > PORT epb_r_w_n = epb_r_w_n > > PORT epb_be_n = epb_be_n > > PORT epb_addr = epb_addr > > PORT epb_doe_n = epb_doe_n > > PORT epb_data_oe_n = epb_data_oe_n > > PORT epb_data_i = epb_data_i > > PORT epb_data_o = epb_data_o > > PORT epb_rdy = epb_rdy > > END > > > > BEGIN epb_infrastructure > > PARAMETER INSTANCE = epb_infrastructure_inst > > PARAMETER HW_VER = 1.00.a > > PORT epb_data_oe_n_i = epb_data_oe_n > > PORT epb_data_out_i = epb_data_o > > PORT epb_data_in_o = epb_data_i > > PORT epb_data_buf = epb_data > > END > > > > BEGIN sys_block > > PARAMETER INSTANCE = sys_block_inst > > PARAMETER HW_VER = 1.00.a > > PARAMETER BOARD_ID = 0xbabe > > PARAMETER REV_MAJOR = 0x1 > > PARAMETER REV_MINOR = 0x0 > > PARAMETER REV_RCS = 0x0 > > PARAMETER RCS_UPTODATE = 0x0 > > PARAMETER C_BASEADDR = 0x00000000 > > PARAMETER C_HIGHADDR = 0x0000FFFF > > BUS_INTERFACE SOPB = opb0 > > PORT OPB_Clk = epb_clk > > PORT soft_reset = soft_reset > > PORT irq_n = ppc_irq_n > > PORT app_irq = 0x0000 > > #PORT fab_clk = sys_clk > > PORT fab_clk = sys_clk > > END > > > > > > > > ############################################## > > # User XSG IP core # > > ############################################## > > > > BEGIN small_test > > PARAMETER INSTANCE = small_test_XSG_core_config > > PARAMETER HW_VER = 1.00.a > > PORT clk = sys_clk > > PORT small_test_one_GbE_app_dbg_data = small_test_one_GbE_app_dbg_data > > PORT small_test_one_GbE_app_dbg_dvld = small_test_one_GbE_app_dbg_dvld > > PORT small_test_one_GbE_app_rx_badframe = > > small_test_one_GbE_app_rx_badframe > > PORT small_test_one_GbE_app_rx_data = small_test_one_GbE_app_rx_data > > PORT small_test_one_GbE_app_rx_dvld = small_test_one_GbE_app_rx_dvld > > PORT small_test_one_GbE_app_rx_eof = small_test_one_GbE_app_rx_eof > > PORT small_test_one_GbE_app_rx_overrun = > small_test_one_GbE_app_rx_overrun > > PORT small_test_one_GbE_app_rx_srcip = small_test_one_GbE_app_rx_srcip > > PORT small_test_one_GbE_app_rx_srcport = > small_test_one_GbE_app_rx_srcport > > PORT small_test_one_GbE_app_tx_afull = small_test_one_GbE_app_tx_afull > > PORT small_test_one_GbE_app_tx_overflow = > > small_test_one_GbE_app_tx_overflow > > PORT small_test_one_GbE_app_rx_ack = small_test_one_GbE_app_rx_ack > > PORT small_test_one_GbE_app_rx_rst = small_test_one_GbE_app_rx_rst > > PORT small_test_one_GbE_app_tx_data = small_test_one_GbE_app_tx_data > > PORT small_test_one_GbE_app_tx_destip = small_test_one_GbE_app_tx_destip > > PORT small_test_one_GbE_app_tx_destport = > > small_test_one_GbE_app_tx_destport > > PORT small_test_one_GbE_app_tx_dvld = small_test_one_GbE_app_tx_dvld > > PORT small_test_one_GbE_app_tx_eof = small_test_one_GbE_app_tx_eof > > PORT small_test_one_GbE_app_tx_rst = small_test_one_GbE_app_tx_rst > > END > > > > ############################ > > # Simulink interfaces # > > ############################ > > > > # small_test/XSG core config > > > > > > # small_test/one_GbE > > BEGIN gbe_udp > > PARAMETER INSTANCE = small_test_one_GbE > > PARAMETER HW_VER = 1.00.a > > PARAMETER LOCAL_ENABLE = 1 > > PARAMETER LOCAL_MAC = 0x123456789ABC > > PARAMETER LOCAL_IP = 0xC0A8290A > > PARAMETER LOCAL_PORT = 0x10E1 > > PARAMETER LOCAL_GATEWAY = 0x1 > > PARAMETER CPU_PROMISCUOUS = 1 > > PARAMETER DIS_CPU_TX = 0 > > PARAMETER DIS_CPU_RX = 0 > > PARAMETER C_BASEADDR = 0x01000000 > > PARAMETER C_HIGHADDR = 0x01003FFF > > BUS_INTERFACE SOPB = opb0 > > PORT OPB_Clk = epb_clk > > BUS_INTERFACE MAC = mac > > PORT app_dbg_data = small_test_one_GbE_app_dbg_data > > PORT app_dbg_dvld = small_test_one_GbE_app_dbg_dvld > > PORT app_rx_badframe = small_test_one_GbE_app_rx_badframe > > PORT app_rx_data = small_test_one_GbE_app_rx_data > > PORT app_rx_dvld = small_test_one_GbE_app_rx_dvld > > PORT app_rx_eof = small_test_one_GbE_app_rx_eof > > PORT app_rx_overrun = small_test_one_GbE_app_rx_overrun > > PORT app_rx_srcip = small_test_one_GbE_app_rx_srcip > > PORT app_rx_srcport = small_test_one_GbE_app_rx_srcport > > PORT app_tx_afull = small_test_one_GbE_app_tx_afull > > PORT app_tx_overflow = small_test_one_GbE_app_tx_overflow > > PORT app_rx_ack = small_test_one_GbE_app_rx_ack > > PORT app_rx_rst = small_test_one_GbE_app_rx_rst > > PORT app_tx_data = small_test_one_GbE_app_tx_data > > PORT app_tx_destip = small_test_one_GbE_app_tx_destip > > PORT app_tx_destport = small_test_one_GbE_app_tx_destport > > PORT app_tx_dvld = small_test_one_GbE_app_tx_dvld > > PORT app_tx_eof = small_test_one_GbE_app_tx_eof > > PORT app_tx_rst = small_test_one_GbE_app_tx_rst > > PORT app_clk = sys_clk > > PORT mac_tx_rst = small_test_one_GbE_app_tx_rst > > PORT mac_rx_rst = small_test_one_GbE_app_rx_rst > > END > > > > > > > > > > > > > > > > > > On Fri, Jan 11, 2013 at 3:04 AM, Henno Kriel <he...@ska.ac.za> wrote: > >> > >> Hi Ioana > >> > >> I have done 2 successful compiles: one with only a one_GbE yellow block > >> and one with a one_GbE yellow block + ten_GbE. > >> > >> Is it possible to send me your model file to compile? > >> > >> Regards > >> Henno > >> > >> On Fri, Jan 11, 2013 at 5:47 AM, Ioana A Zelko <ize...@mit.edu> wrote: > >>> > >>> Dear Casper Group, > >>> > >>> > >>> We are trying to set up data transmission from the fpga through its > 1gbe > >>> ethernet port. > >>> For this, we tried using the one_GbE block from the library, with its > >>> default settings. > >>> However, when we try to compile a small design that has basically just > >>> the one_GbE with its required logic, > >>> we get this error in the compilation stage: > >>> > >>> > >>> > >>> " > >>> Writing NGC file "../system_gbe1_test_xsg_core_ > >>> config_wrapper.ngc" ... > >>> Total REAL time to NGCBUILD completion: 4 sec > >>> Total CPU time to NGCBUILD completion: 4 sec > >>> > >>> Writing NGCBUILD log file > >>> "../system_gbe1_test_xsg_core_config_wrapper.blc"... > >>> > >>> NGCBUILD done. > >>> INFO:EDK:3509 - NCF files should not be modified as they will be > >>> regenerated. > >>> If any constraint needs to be overridden, this should be done by > >>> modifying > >>> the data/system.ucf file. > >>> > >>> Rebuilding cache ... > >>> ERROR:EDK:440 - platgen failed with errors! > >>> gmake: *** [implementation/system.bmm] Error 2 > >>> ERROR:EDK - > >>> Error while running "gmake -f system.make bits". > >>> Error using gen_xps_files (line 636) > >>> XPS failed. " > >>> > >>> > >>> > >>> Do you have any idea what could be causing this? > >>> We managed to compile a big design that was using the "ten_Gbe_v2" as a > >>> receiver with no problem. > >>> > >>> > >>> Thank you so much for your help! > >>> > >>> Ioana and Jeff > >> > >> > >> > >> > >> -- > >> Henno Kriel > >> > >> DSP Engineer > >> Digital Back End > >> meerKAT > >> > >> SKA South Africa > >> Third Floor > >> The Park > >> Park Road (off Alexandra Road) > >> Pinelands > >> 7405 > >> Western Cape > >> South Africa > >> > >> Latitude: -33.94329 (South); Longitude: 18.48945 (East). > >> > >> (p) +27 (0)21 506 7300 > >> (p) +27 (0)21 506 7365 (direct) > >> (f) +27 (0)21 506 7375 > >> (m) +27 (0)84 504 5050 > > > > >
