I have a ROACH board and am using a design I got from another ROACH person. The design uses a lookup table stored in a dram. The software interface is used to load the dram with the data. later, the dram is read out to stream data to MKID DAC board.
Questions: I have my FPGA running at 128MHz. The DRAM runs at 200MHz. What speed does the dataout port of the dram spit data? Does it just work at 128MHz and I get a 144 bit word every clock at 128MHz? Or is the dataout running at 200MHz, where I have to send data to FIFO at 200MHz, then readout the FIFO at 128MHz? Do I really care about the FIFO clock rate as long as I can get data at 128MHz? >From the dram docs on the web: " To read data out of the DRAM, hold 'RWn' high, keep the address constant for two FPGA clock cycles, and toggle the 'cmd_valid' pin every clock. Note that a new word will be available on the 'data_out' pin on every clock cycle. 'rd_valid' will frame valid output data some indeterminate number of clock cycles after the read 'cmd_valid' toggles. 'cmd_ack' is high unless an attempt to write a command into the input FIFO failed, at which point it will go low synchronously with the issuing of the failed command. " So if I wish to read out address 0, 1, 2, ....I have to keep the address constant for 2 fpga clocks. Then I can only read out dram at fpga_clock/2? Or, do I toggle cmd_valid, to get address 0, 1 at the 128MHz fpga clock. Now I have to set the addr to 2 and toggle cmd_valid again. IN this case, I still cannot readout the dram at 128MHz. Or perhaps I toggle cmd_valid forever and get data from address 0,1,2,3... on every fpga clock cycle? All of the example model files run at 200MHz, and dram is at 200MHz. So it is not much help. Tim Madden
