Hi Weiwei, Have you calibrated the MMCM phase using test vectors? The following repository hosts Python/corr code that may be helpful to you:
https://github.com/sma-wideband/adc_tests I've recently updated the README, please see the "Calibrating the data-to-clk" for instructions on how to use the code. I believe this may correct the bit errors you're seeing. Note: this code assumes that your bitcode has a snapshot hooked up to your raw ADC output _after_ it's been converted to signed two's. Alternatively there is some code out there (I believe written by Jack Hickish) that adjusts the IODELAYs on each data bit to correct for capture errors. Lastly, please keep in mind that this ADC has four interleaved cores each with their own phase, bias, and gain differences. These may need to be adjusted as well depending on your application. Best, Rurik On Jan 30, 2014 6:36 PM, "Weiwei Sun" <su...@uw.edu> wrote: > Hi Rurik and Casparians, > > I have a problem with the data out of the adc5g yellow block and 2's > complementary change and captured by a snapshot. It seems there is bit > errors during the transmission, or it could be some other problem. This is > roach2 with an adc5g clocked at 1400MHz, 2-channel, Nondemux (1:1) mode. > > I tested it with a 175MHz sinusoid wave generated by a signal generator. > The samples are predicted to be constant for every stream of the total 8 > output streams with amplitude 32 within range (-128, 127), but I saw a lot > of bit errors (bit flip? ). Attached are the time series of the 8 streams. > Has anyone experienced this weird data? I'm appreciated of your attention > and advice! Thanks! > > Weiwei > >
