On Tue, Feb 25, 2014 at 7:43 AM, G Jones <glenn.calt...@gmail.com> wrote: > Hi Marc, > Thanks for the reply. I would have expected that selecting the 64 MB chunk > with the dram_controller register as described in the DRAM block > documentation on the wiki would get around any such PPC address space > limitation. Is that not the case?
I think that should indeed be the case - I had forgotten that the base+offset scheme had already been implemented quite some time ago. A note though: On the other side of the FPGA, there isn't that much memory to go around either - so where possibly try and send it out (or process it) in smaller pieces regards marc
