Hi all again. I'm trying to understand why when I set the bit file to the FPGA IBOB, change the IBOB IP address 169.254.177.32 to 192.168.49.32, port 7?
I updated my libraries with https://casper.berkeley.edu/wiki/images/6/60/6q05d3bE_udp_patch.tar.gz Then I compiled the new design. I got the bit file to use UDP. After programming the FPGA with the new bit file happens the IP address change. Is this normal behavior? Best Regards Rolando Paz
