Hi everybody. I have a problem building a digital filter before the data enter to the PFB on my design. I need to design an FIR band pass filter but i don know if there is a well known way to do this (maybe there is a block pre-designed).
i found a FIR compiler on the xilinx blockset and i load the fir coefficients from the fda tool without problems. I Have 8 samples in parallel coming from the ADC each clock FPGA clock cicle. it seems to me the problem is that the xilinx FIR compiler is filtering each path independently, in other words not considering the 8 inputs in parallel like 8 samples of a signal each taken at the same rate sample. i hope some one understand the problem and could have a solution. Have anyone has the same problem? Thank you -- *Edgardo Huaracán Durán* *Memorista Observatorio Astronómico Nacional* *Universidad de Chile*
