Hi all, I have a yellowblock for an ADC (made by someone else--I don't know how to write yellowblocks) meant to clock the design off adc0clk.
Designs using this yellowblock work fine with ISE 11, but with ISE 14 they manage to get through compilation successfully, but when running don't seem to allow the FPGA to receive a clock. I suspect there is something wrong with the yellowblock here, but I don't know where to look or what to look for. Has anyone seen anything like this? -Alex
