Hi all,
Do anyone here have any experiences in Broadcom's PHY chip BCM8747? I have a Xilinx Virtex 6 FPGA board and a 10 gigabit ethernet expansion board that has 4 PHY chips (BCM8747). There are ZD connectors between the two boards. And I came across some problems. I am sure that the supply voltage and the reference clock (156.25 MHz) of the PHY are OK. And I also have made a testing of eye diagram for the trasmitter and the reciever of XAUI. Both of the eye's width and height meet the requirements of BCM8747 data sheet. But it has a problem in sychoronization and alignment of the four lanes. The four lanes(one port) can't be sychoronized and aligned even I configured the PHY to the independent lane loopback operation mode(It connects the XAUI deserializer output directly to the XAUI serializer input). I also tried to configure the PHY to be 1 Gbe bypass mode and made a loopback. It was not linked up, either. Has anyone met problems like these yet? Thank you very much! Best wishes, Lin
