Hi, Peter, I created a wiki page describing the EQ settings:
https://casper.berkeley.edu/wiki/PAPER_Correlator_EQ For the -1 speed grade FPGAs on the RPACH2, the MMCMs on the ROACH2 cannot be configured in "HIGH Bandwidth Mode" when the input clock frequency is 250 MHz, so they must run in "LOW Bandwidth Mode" at that frequency. Running with the MMCMs in "LOW bandwidth mode" does not give reliable capture of the high speed serial data bits that come from the ADC16 cards. Maybe it is somehow possible to coax the MMCM into high bandwidth mode with a 250 MHz sample clock, but we gave up trying. The ADC16 yellow block in 16-input mode supports a maximum sample rate of 240 MSPS. This is explained here: https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Operating_Modes It could probably use a little clarification that "16 inputs by 250 MSPS by 8 bits" is the ADC chip's max sample rate, but that rate is not supported by the ADC16 yellow block gateware due to limitations in the -1 speed grade FPGA MMCM. Dave On Nov 25, 2014, at 1:01 AM, Peter Niu wrote: > Hi Dave, > Thanks for your help! I have a question about EQ model.If I gusee right,the > EQ model have a cability to initial the value for every input signal channel. > The paper_feng_init.rb could use > ./paper_feng_init.rb -e eq_value > to initial the value of the EQ.I don't quite understand how it could initial > each channel.I think the eq_value of each channel is different,but we just > got one value here. > I got from former mails on mail-list,the value of the EQ could got in a > method : set the value to zero first, turn the value bigger,and stop when the > data value of received packet is not zero,thenThe EQ value is what we > need.Is this method right? > I have a second question to ask you.Our project now need up the clock rate to > 250Mhz,I found the bof file could run correctlly in 250Mhz clock rate.Do you > think It is ok for a long time running?I try to change the model to 250Mhz > when I compiled,but bof file could not compiled.The matlab said it is a ADC > block problem. > Best wishes > Peter > > >
