Hi, All, In our model, We need ADC clock frequency up to 250Mhz. Our ADC boards are ADC16*250-8.We are using adc16*250-8 yellow block in our model modified based PAPER model .However when I changed the XSG core config/User IP Clock Rate(MHz) to 250 Mhz and System Generator/FPGA Clock Period(ns) to 4ns, it could not create bof file,something like the following:
ERROR:LIT:667 - Block 'MMCM_ADV symbol "physical_group_roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl8511_250port_ adc1_adc16x250_8/bufg_i<3>/roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl85 11_250port_adc1_adc16x250_8/adc_mmcm_0/mmcm_adv_inst" (output signal=roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl8511_250port_adc1_adc1 6x250_8/bufg_i<3>)' has its target frequency, FVCO, out of range. Valid FVCO range for speed grade "-1" is 600MHz - 1200MHz. The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD attribute may have been set by ngdbuild based on the user specified PERIOD constraint. The current calculated FVCO is 1250.000000 MHz. Reference the V6 architecture Users Guide or search the Xilinx Answer Records database for the error code. Now, The system work in 250Mhz clock rate while the model bof file is crearted in 200Mhz. It looks no problem in sending the correct data packets, but I am not sure whether it run normally.In theory , the input data rate is 250Mhz*8bits*32=64Gbits/s,after fft, EQ ,the data rate becomes 32Gbits/s,we have 4 10Gbe ports to send out data.Each ports will have32/4=8Gbits/s,(if we use 200MHz,this data rate is about 6.4Gbits/s )I don't know whether it is ok for the transition capability of the 10Gbe NICs(10Gbits/s). Could anyone help me please? Thanks! peter
