Hello guys, Is there any clear documentation on the working of the 10Gbe core's second version ? Sometimes I see that the design (i.e. tx_valid, tx_eof) work fine in simulation, but the core does not transmit when testing in real time. Some times adding a few delay blocks sets the transmission going.
What're the general requirements/precautions while designing a 10G incorporated design ? Is there some warnings/ optimizations that must be watched out for before synthesis/implementation ? In short, how to build a *reliable* 10G design ? Thanks in advance ! -- the giver of moksha
