Dear Casperites,
I, once again, need your wisdom. I'm trying to do floorplanning on a
model, but whenever I create a new project with Xilinx Planahead the
model fails to load. Just to be sure I'm not doing something wrong I'll
detail my workflow:
1. I compile a Simulink model using Matlab/casper_xps. The model
compiles successfully.
2. I open PlanAhead with: "source setting64.sh && sudo planAhead" in the
Xilinx installation folder.
3. "Create a new project" -> "Import ISE & Place and Route Results"
4. In add netlist source list: "Add File" ->
"<myProject>/XPS_ROACH2_base/implementation/system.ngc", "Import
Directories" -> "<myProject>/XPS_ROACH2_base/implementation/"
5. In add constraints: "Add File" ->
"<myProject>/XPS_ROACH2_base/implementation/system.ucf"
6. In default part I choose: "xc6vsx475tff1759-1"
7. In import ISE implementation results: "Placement file" ->
"<myProject>/XPS_ROACH2_base/implementation/system_map.ncd", "Import
timing" -> "<myProject>/XPS_ROACH2_base/implementation/system.twx"
8. After doing this, the project starts loading the files and I get this
error:
ERROR: [Designutils 20-662] Internal error: 'Cannot place carry chain
instance
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000002c
at (SLICE_X107Y155): Could not legally place instance
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000002c
at SLICE_X107Y155 since it belongs to a shape containing instance
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000001b.
The shape requires relative placement between
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000002c
and
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000001b
that cannnot be honored because it would result in an invalid location
for
kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_XSG_core_config/kestfilt_4096ch_600mhz1_x0/fft_wideband_real0_3bb28f4f1a/fft_direct_2a29a9ae17/butterfly2_0_74870afb03/bus_convert_a7eae3d1b2/conv2_4beea44e63/convert_8b81baa718/adder/comp9.core_instance9/blk00000001/blk0000001b.'
And four other similar errors.
I'm using Matlab 2013a, Xilinx ISE Design Suite 14.7, and the latest
version of casper-astro/mlib_devel from github in Debian Stretch. I'm
really confused by this error, it seems to be a placement error, but it
doesn't make sense because I could successfully compiled with
casper_xps. Googling the problem I only found this link:
https://forums.xilinx.com/t5/Synthesis/Planahead-Cannot-place-carry-chain-instance/td-p/742833
which didn't helped me too much.
Has anyone encountered this same problem?
Franco
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