Hi Amit
When I update the design I get the following:
Warning: The model 'test' does not have continuous states, hence Simulink
is using
the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can
disable this
diagnostic by explicitly specifying a discrete solver in the solver tab of
the
Configuration Parameters dialog, or by setting the 'Automatic solver
parameter
selection' diagnostic to 'none' in the Diagnostics tab of the Configuration
Parameters dialog
Warning: Using a default value of 0.2 for maximum step size. The
simulation step
size will be equal to or less than this value. You can disable this
diagnostic by
setting 'Automatic solver parameter selection' diagnostic to 'none' in the
Diagnostics page of the configuration parameters dialog
And when I run casper_xps I get this:
>> casper_xps
Detected Linux OS#############################
## System Update ##
#############################
Warning: The model 'test' does not have continuous states, hence Simulink
is using
the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can
disable this
diagnostic by explicitly specifying a discrete solver in the solver tab of
the
Configuration Parameters dialog, or by setting the 'Automatic solver
parameter
selection' diagnostic to 'none' in the Diagnostics tab of the Configuration
Parameters dialog
> In gen_xps_files at 202
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Using a default value of 0.2 for maximum step size. The
simulation step
size will be equal to or less than this value. You can disable this
diagnostic by
setting 'Automatic solver parameter selection' diagnostic to 'none' in the
Diagnostics page of the configuration parameters dialog
> In gen_xps_files at 202
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
#############################
## Block objects creation ##
#############################
######################
## Checking objects ##
######################
Running system generator ...
Warning: The model 'test' does not have continuous states, hence Simulink is
using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can
disable this diagnostic by explicitly specifying a discrete solver in the
solver
tab of the Configuration Parameters dialog, or by setting the 'Automatic
solver
parameter selection' diagnostic to 'none' in the Diagnostics tab of the
Configuration Parameters dialog
> In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlCompileGenerateMdl.p>xlCompileGenerateMdl
at 203
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 302
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Using a default value of 0.2 for maximum step size. The
simulation step
size will be equal to or less than this value. You can disable this
diagnostic
by setting 'Automatic solver parameter selection' diagnostic to 'none' in
the
Diagnostics page of the configuration parameters dialog
> In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlCompileGenerateMdl.p>xlCompileGenerateMdl
at 203
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 302
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Possible deprecated use of get on a Java object with an HG Property
'UserData'.
> In xlNGCPostGeneration at 57
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlruntargetfcn.p>xlruntargetfcn
at 12
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 478
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Possible deprecated use of set on a Java object with an HG Property
'UserData'.
> In xlNGCPostGeneration at 60
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlruntargetfcn.p>xlruntargetfcn
at 12
In
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 478
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
XSG generation complete.
#########################
## Copying base system ##
#########################
Copying base package from:
/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH_base
########################
## Copying custom IPs ##
########################
##########################
## Creating Simulink IP ##
##########################
##########################
## Creating EDK files ##
##########################
Warning: git not found.
> In git_info at 17
In git_write_info at 2
In gen_xps_files at 554
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
#########################
## Elaborating objects ##
#########################
##############################
## Preparing software files ##
##############################
#########################
## Running EDK backend ##
#########################
Warning: File
'/home/dserver/Simulink/test/XPS_ROACH_base/implementation/system.bit' not
found.
> In gen_xps_files at 666
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: File
'/home/dserver/Simulink/test/XPS_ROACH_base/implementation/download.bit' not
found.
> In gen_xps_files at 667
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Xilinx Platform Studio
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Loading xmp file system.xmp
INFO:EDK - This project was created with version older than EDK 14.7!!
INFO:EDK - XPS will update the project to EDK 14.7
INFO:EDK - Your current files will be saved with .<old version> extension
Reving up design to EDK 14.7...
WARNING: log file system.log not found
Xilinx EDK 11.1
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.10
Creating backup of system.mhs as system_mhs.10
sh: dos2unix: command not found
Creating backup of system.mss as system_mss.10
Format revision from 10.1 to 11.1 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.2
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.1
Creating backup of system.log as system_log.11.1
Creating backup of system.mhs as system_mhs.11.1
Creating backup of system.mss as system_mss.11.1
Format revision from 11.1 to 11.2 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.3
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.2
Creating backup of system.log as system_log.11.2
Creating backup of system.mhs as system_mhs.11.2
Creating backup of system.mss as system_mss.11.2
Format revision from 11.2 to 11.3 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.4
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.3
Creating backup of system.log as system_log.11.3
Creating backup of system.mhs as system_mhs.11.3
Creating backup of system.mss as system_mss.11.3
Format revision from 11.3 to 11.4 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.5
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.4
Creating backup of system.log as system_log.11.4
Creating backup of system.mhs as system_mhs.11.4
Creating backup of system.mss as system_mss.11.4
Format revision from 11.4 to 11.5 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.0
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.11.5
Format revision from 11.5 to 12.0 completed.
No changes to design files while updating the design from 11.5 to 12.0
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.0
Format revision from 12.0 to 12.1 completed.
No changes to design files while updating the design from 12.0 to 12.1
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.2
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.1
Format revision from 12.1 to 12.2 completed.
No changes to design files while updating the design from 12.1 to 12.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.3
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.2
Format revision from 12.2 to 12.3 completed.
No changes to design files while updating the design from 12.2 to 12.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.4
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.3
Format revision from 12.3 to 12.4 completed.
No changes to design files while updating the design from 12.3 to 12.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.4
Writing system.xmp ...
EDK version 13.1 UPDATE:
Removing Software Project information from system.xmp
Removing XmdStub and BootLoop information from system.xmp
Elf file information is preserved based on InitBram value..
Format revision from 12.4 to 13.1 completed.
Design files have changed while updating the design from 12.4 to 13.1
Creating a back up of 12.4 design files...
Creating backup of system.mhs as system_mhs.12.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.2
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.1
Format revision from 13.1 to 13.2 completed.
No changes to design files while updating the design from 13.1 to 13.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.3
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.2
Format revision from 13.2 to 13.3 completed.
No changes to design files while updating the design from 13.2 to 13.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.4
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.3
Format revision from 13.3 to 13.4 completed.
No changes to design files while updating the design from 13.3 to 13.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.4
Format revision from 13.4 to 14.1 completed.
No changes to design files while updating the design from 13.4 to 14.1
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.2
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.1
Format revision from 14.1 to 14.2 completed.
No changes to design files while updating the design from 14.1 to 14.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.3
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.2
Format revision from 14.2 to 14.3 completed.
No changes to design files while updating the design from 14.2 to 14.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.4
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.3
Format revision from 14.3 to 14.4 completed.
No changes to design files while updating the design from 14.3 to 14.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.5
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.4
Format revision from 14.4 to 14.5 completed.
No changes to design files while updating the design from 14.4 to 14.5
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.6
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.5
Format revision from 14.5 to 14.6 completed.
No changes to design files while updating the design from 14.5 to 14.6
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.7
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.6
Format revision from 14.6 to 14.7 completed.
No changes to design files while updating the design from 14.6 to 14.7
Moving all revup related files to 'revup' folder...
Format revision of project to EDK 14.7 completed
Overriding IP level properties ...
Computing clock values...
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
core
and cores connected to it.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor epb_opb_bridge_inst
(0000000000-0x0000ffff) sys_block_inst opb0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++ WARNING !!! +++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
WARNING:EDK - Processor epb_opb_bridge_inst has no memory mapped at its
reset
vector.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
C_NUM_MASTERS value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
ta/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
C_NUM_SLAVES value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
ta/opb_v20_v2_1_0.mpd line 75
Checking platform address map ...
XPS% Evaluating file run_xps.tcl
Xilinx Port::Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f system.make bits".
Error using edit (line 66)
File 'implementation/system.twr' not found.
>>
Could it be the pcores?
Thanks for the help
Heystek
On Mon, Aug 28, 2017 at 10:23 AM, Amit Bansod <aban...@mpifr-bonn.mpg.de>
wrote:
> Hi,
>
> Can you try to update design (ctrl + D) to see if you get more information
> on the error?
> Cheers,
> Amit
>
>
> On 28 August 2017 09:10:56 CEST, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>>
>> Hi Jack
>>
>> I have tried that but it still does not work. I have tried it with all
>> casper tutorials. The file “gen_xps_files.m” gives the problem. It is this
>> three veriables
>>
>> xps_objs
>> custom_xps_objs
>> core_types
>>
>> [image: Inline image 1]
>>
>> It breaks at line 255
>>
>> I cant figure out what is causing it.
>>
>> Heystek
>>
>> On Fri, Aug 25, 2017 at 6:45 PM, Jack Hickish <jackhick...@gmail.com>
>> wrote:
>>
>>> Weird. I'm guessing that is a software register? if you select the block
>>> that's throwing the error, then in matlab type "update_casper_block(gcb)"
>>> (which will delete that block and replace it with a fresh copy from the
>>> library) does that help at all.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Fri, 25 Aug 2017 at 04:21 Heystek Grobler <heystekgrob...@gmail.com>
>>> wrote:
>>>
>>>> Good day everyone!
>>>>
>>>> I have one more weird problem. If I run casper_xps and start the
>>>> compilation, everything works until the file creation part. I keep getting
>>>> this error:
>>>>
>>>> casper_xps
>>>> Detected Linux OS#############################
>>>> ## System Update ##
>>>> #############################
>>>> Warning: The model 'tutorial1' does not have continuous states, hence
>>>> Simulink is
>>>> using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You
>>>> can disable
>>>> this diagnostic by explicitly specifying a discrete solver in the
>>>> solver tab of the
>>>> Configuration Parameters dialog, or by setting the 'Automatic solver
>>>> parameter
>>>> selection' diagnostic to 'none' in the Diagnostics tab of the
>>>> Configuration
>>>> Parameters dialog
>>>> > In gen_xps_files at 202
>>>> In casper_xps>run_Callback at 155
>>>> In casper_xps at 88
>>>> In @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
>>>> ata,guidata(hObject))
>>>> Warning: Using a default value of 0.2 for maximum step size. The
>>>> simulation step
>>>> size will be equal to or less than this value. You can disable this
>>>> diagnostic by
>>>> setting 'Automatic solver parameter selection' diagnostic to 'none' in
>>>> the
>>>> Diagnostics page of the configuration parameters dialog
>>>> > In gen_xps_files at 202
>>>> In casper_xps>run_Callback at 155
>>>> In casper_xps at 88
>>>> In @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
>>>> ata,guidata(hObject))
>>>> #############################
>>>> ## Block objects creation ##
>>>> #############################
>>>> Problem with XPS: tag block: tutorial1/counter_value
>>>>
>>>> Error using gen_xps_files (line 255)
>>>> Error found during Object creation.
>>>>
>>>> Do anyone perhaps know what is going on?
>>>>
>>>> Thanks for the help
>>>>
>>>> --
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>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>
>>>
>>
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