Hi James,

I tried it using the version of casperfpga you suggested. The same error is
returned.

I'm attaching the python code that I'm using for programming the board.

-
Regards,

Mugundhan V.

On Thu, Oct 12, 2017 at 5:24 PM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Mugundhan,
>
> Casperfpga is a work in progress and unfortunately some of the more recent
> developments will have broken compatibility with ROACH1. Its main focus at
> the moment is SKARAB / ROACH2.
>
> I use the following commit to work on ROACH1:
> avnuser@planck:~/SKASoftware/casperfpga$ git show
> commit 475ed6826b893230d62da8c7dcdcc2541bea83cf
> Merge: 9835009 7402b29
> Author: Paul Prozesky <pa...@ska.ac.za>
> Date:   Fri Mar 4 17:27:09 2016 +0200
>
>     Merge branch 'devel' of github.com:ska-sa/casperfpga into devel
>
> Try installing casperfpga from that particular git commit and you'll
> likely be more successful.
>
> Also, before you use the fpga.program() function, you need to set the bof
> file in the system information - I think I have mentioned how to do this in
> the history of the mailing list somewhere before.
>
> Let me know if it works.
>
> Regards,
> James
>
>
> On Thu, Oct 12, 2017 at 12:35 PM, Mugundhan vijayaraghavan <
> v.vaishnav151...@gmail.com> wrote:
>
>> And I'm using the latest version of casperfpga library and katcp version.
>>
>> On Thu, Oct 12, 2017 at 3:56 PM, Mugundhan vijayaraghavan <
>> v.vaishnav151...@gmail.com> wrote:
>>
>>> Hello James,
>>>
>>> I'm attaching the model files of the first and the second designs, along
>>> with the bof and the fga files. I used the ipython terminal for programming
>>> the fpga in both cases. The error I obtained is attached in a text file.
>>>
>>> Hope this helps,
>>>
>>> Thank you,
>>>
>>> Mugundhan V.
>>>
>>>
>>>
>>> On Thu, Oct 12, 2017 at 3:49 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Mugundhan,
>>>>
>>>> Please describe your context a bit more - what libraries are you using?
>>>> Please also paste the error that you get? (and perhaps the code you used to
>>>> generate the error.)
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Thu, Oct 12, 2017 at 12:17 PM, Mugundhan vijayaraghavan <
>>>> v.vaishnav151...@gmail.com> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I'm facing a strange problem. I have an iADC, which I've connected to
>>>>> roach1 and have compiled a program to acquire raw samples from it. The
>>>>> simulation, compilation and generation works fine and I get the bof and 
>>>>> the
>>>>> fpg files, which i place in their respective locations, and the ROACH gets
>>>>> programmed well.
>>>>>
>>>>> I also developed a iADC spectropolarimeter and generated the fpg and
>>>>> bof files and placed them in their locations, but now when I try
>>>>> programming the ROACH, i get Katcp request time out error. If i reprogram
>>>>> the first bof file, it works fine, but repeated compilation and program
>>>>> cycles have failed for hte second model, with the same katcp request 
>>>>> failed
>>>>> error.
>>>>>
>>>>> Can someone kindly guide me solving it ?
>>>>>
>>>>> Thank you,
>>>>>
>>>>> --
>>>>> V. Mugundhan
>>>>> SRF, IIA
>>>>>
>>>>> --
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>>>>
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>>>
>>>
>>>
>>> --
>>> V. Mugundhan
>>> SRF, IIA
>>>
>>
>>
>>
>> --
>> V. Mugundhan
>> SRF, IIA
>>
>
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-- 
V. Mugundhan
SRF, IIA

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import matplotlib.pyplot as plt
import numpy as np
import scipy as sp
import os
import time
import casperfpga
import sys
import logging

def exit_fail():
    print 'FAILURE DETECTED. Log entries:\n'
    try:
        fpga.stop()
    except: pass
    raise
    exit()

def exit_clean():
    try:
        fpga.stop()
    except: pass
    exit()

fpga = casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
if (fpga.is_connected() == True):
    print 'Connected to the FPGA '
else:
    print 'Not connected to the FPGA'

try:	
	ch=raw_input('Want to program ROACH ?')
	if (ch=='Y' or ch=='y'):
		print 'Programming ROACH . . . \n'
		boffile='ver1_stk_i_400mhz_2_2017_Oct_12_2039.bof'		
		fpga.system_info['program_filename'] = boffile
		fpga.program()
		time.sleep(5)
		print '...Done...'
	else:
		print 'continuing with existing configuration . . .\n'
	
	fpga.write_int('acc_reset',0);
        time.sleep(2)	
	fpga.write_int('rst10g',1);
        fpga.write_int('rst10g',0);
	time.sleep(1)	
	fpga.write_int('acc_len',20480);
	fpga.write_int('sync_pulse',1); #number of spectra to accumulate
	time.sleep(1)
	#fig=plt.figure()
	#plt.clf()
	#plt.ion()	
except KeyboardInterrupt:
		exit_clean()

exit_clean()
			

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