Correction: by "exactly that", I mean building a radio astronomy targeted board around the RFSoC chip, but not necessarily CASPER-ised....

On 3/19/2018 1:48 PM, Karl Warnick wrote:
I have heard, if I remember correctly, that CSIRO is doing exactly this. If anyone has details, perhaps they could let the group know. If not, I can probably trace the source and find out.

They are expensive chips, but maybe lower rate, lower cost versions will be forthcoming.

Karl

On 3/16/2018 1:10 AM, Francois Kapp wrote:
The timing and availability might be a factor, but it would be great if "someone" had the energy to "CASPER-ise" a Xilinx RFSoC development board. They have up to 16 ADC's that may be overkill in the sample rate department, but it is an interesting platform.  Maybe development boards are available?

On 16 Mar 2018 07:05, "Jack Hickish" <jackhick...@gmail.com <mailto:jackhick...@gmail.com>> wrote:

    Hi Karl,

    On Thu, 15 Mar 2018 at 21:59 Karl Warnick <warn...@ee.byu.edu
    <mailto:warn...@ee.byu.edu>> wrote:

        Hi all,

        I have a non-astronomical comms antenna array project that
        does not have
        detailed specs for bandwidth and number of antenna elements.
        I need to
        build a programmable platform that I can use for multichannel
        sampling
        and real time DSP.

        Our group has considerable experience with ROACH based
        systems over the
        years and hybrid FPGA - GPU architectures, but the students
        with much of
        the expertise have graduated and moved on, as students tend
        to do. We
        have an x64 board and ROACH that on paper could do the job,
        but the
        hardware seems old enough now that I wonder if it might be
        wise to move
        to a new platform for my new project. We also like the easier
        programmability of GPUs for matrix based array signal processing
        algorithms. We also have a system with digitizers, polyphase
        filterbanks
        running on ROACH boards, ethernet switch, and HPCs with GPUs,
        but that
        system is in operation at GBO and is probably overkill for
        the current
        project.

        This leads to my question. To realize a system with 16 analog
        channels
        and analog bandwidth ranging between a few MHz up to 100 MHz
        (I realize
        that this is a rather ill defined range, but I feel fortunate
        to have
        the flexibility), that can do digitization, filterbank to
        separate into
        frequency channels, and enough processor power for real time XB
        (correlator/beamformer) type signal processing, with current
        CASPER
        hardware, what would be the ideal, recommended hardware setup?


    I think your options here are either a/some SNAP board(s) -- 12
    ADC channels at up to 250 MSample/s sampling rate, or a ROACH2 +
    adc16 card -- 16 channels at up to 250MSample/s. Either would
    give you Ethernet output on SFP+ connectors. SNAP can do up to
    20Gb/s output, ROACH2 up to 80Gb/s.
    In either case, there should be some simulink designs you could
    use as a starting point, from PAPER/HERA or other projects.

    Cheers
    Jack


        The relatively modest bandwidth requirement may also point to a
        commercial FPGA/ARM core board with an ADC expansion board,
        and I'm
        pursuing that path as well. From another project, I have an
        expansion
        board of our own design with eight ADC channels that plugs into a
        microZED board, which actually comes somewhat close to
        meeting the
        current requirements. Expanding the ADC board and moving to a
        bigger
        commercial digital board is an option.

        Thanks to all for any feedback!

        Best,
        Karl

        --
        Karl F. Warnick
        Department of Electrical and Computer Engineering
        Brigham Young University
        459 Clyde Building
        Provo, UT 84602
        (801) 422-1732





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459 Clyde Building
Provo, UT 84602
(801) 422-1732






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Karl F. Warnick
Department of Electrical and Computer Engineering
Brigham Young University
459 Clyde Building
Provo, UT 84602
(801) 422-1732





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