Hi Peix Xin,

That all should be ok. Are you able to confirm that the ADC / clock are
definitely working using a Roach2?

Cheers
Jack

On Mon, 8 Oct 2018, 9:11 pm pei...@xao.ac.cn, <pei...@xao.ac.cn> wrote:

> Hi Jack,
>
> Our ADC card is a Demux 1:1 version, see attachment 1. Will this be the
> problem?
> And the mlib_devel is the same one we used for Crab design.
>
> The ADC yellow block and MSSGE block settings see attach 2 and 3 .
>
> The clock signal is from Valon 5008 and inject to the Clock SMA connector
> of ADC.
>
> Best wishes,
> Pei Xin
>
>
> *From:* Jack Hickish <jackhick...@gmail.com>
> *Date:* 2018-10-08 22:19
> *To:* casper <casper@lists.berkeley.edu>
> *Subject:* [CASS SPAM]Re: [casper] ADC5G on SNAP
>
> Hi Peix Xin,
>
> That should work. What mlib_devel are you using?
> Is your ADC card a demux 1 version?
>
> What ADC yellow block settings?
> What snap MSSGE block settings (should be clocking from adc0_clk)
>
> Are you applying a clock to the ADC card - you can't use the on-board
> synthesiser with an external ADC.
>
> Cheers
> Jack
>
> On Mon, 8 Oct 2018, 6:38 am pei...@xao.ac.cn, <pei...@xao.ac.cn> wrote:
>
>> Hi Jack,
>>
>> We want use ADC5G card on SNAP board, is there any setting to switch on
>> ZDOK connector?
>> The programming is done, however, it returnned 0.0 when we try 
>> fpga.est_brd_clk()
>> to check the FPGA's clock.
>>
>> Best wishes,
>> Pei Xin
>>
>> ------------------------------
>>
>> ==========================================                           
>> 裴鑫 (Xin Pei)
>> 中国科学院新疆天文台
>> Xinjiang Astronomical Observatory, CAS
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