Hi Jack, Thank you so much for your reply. It clarifies a lot of things.
And, to second the request from Vinand, do you have any suggestions for a relatively low-cost device or technique in order to obtain a reference signal and PPS provider? Cheers, Nitish On Fri, Oct 19, 2018 at 7:57 PM Jack Hickish <jackhick...@gmail.com> wrote: > Hi Nitish, > > Hope you don't mind, but I'm taking this back on the list. > > Your understanding of the PPS signal is correct. > > If you with to use the on-board SNAP ADCs, you have two clocking options, > both of which require an external signal to be provided. > > 1) Provide a timing reference (usually, but not necessarily, 10 MHz) to > the on-board synthesizer, and use that to generate your sampling clock > (see, for example > https://github.com/casper-astro/tutorials_devel/blob/ba099ddefc8c1f74725bc3d5531e9641c1a41dee/vivado/snap/tut_spec/snap_tut_spec.py#L99 > ) > > 2) Provide a clock at your sampling rate direct to the board. > > You only need to do one of these -- you should either provide a > synthesizer reference on SMATP14 **or** a clock at your sampling rate on > SMATP15. > > The synthesizer on the board has two outputs. One is used to drive the > ADCs (option 1, above) the other is available on the SMA connector you > mention. It's not obvious to me how that would be useful in most > situations, though potentially you could use it to clock an external ZDOK > ADC card. I've only ever used this output for debugging the synthesizer. I > think python software probably exists to control this output (see > https://github.com/casper-astro/casperfpga/blob/master/src/synth.py) > though I don't know how complete it is. > > Hope that helps a bit, > > Jack > > On Fri, 19 Oct 2018 at 04:58 Nitish Ragoomundun < > nitish.ragoomun...@gmail.com> wrote: > >> >> Hello, >> >> We recently bought a SNAP board and we are having a few issues about >> clocking. I just mailed the CASPER group and got a few interesting >> responses. We would just like to have an explanation about the external >> clock inputs to the board. >> >> Our project basically consists in building a low-frequency array for the >> observation of the deuterium hyperfine line at 327.4 MHz with a bandwidth >> of 250 kHz. The SNAP boards will operate at full 12 channels input, thus >> the ADCs at 250 MSps. We will subsequently decimate the data rate, as our >> working bandwidth is narrow. >> >> Now, can you please shed some light on these statements from the SNAP >> wiki (https://casper.berkeley.edu/wiki/SNAP): >> >> - * Digital 1 PPS: 50 ohm single-ended LVTTL logic levels * >> - >> *... * >> - * External ADC clock: 50 ohm single-ended about +2 dB* >> - >> *... * >> - * External reference for on-board frequency synthesizer: 50 ohm >> about +10dBm * >> - *...* >> >> We understand that the Digital 1 PPS is for synchronisation with a time >> server. And, that the external reference for the frequency synthesizer will >> enable all samples acquired from different boards to be phased properly. >> Please correct us if we are wrong. >> >> We would like to know if the external ADC clock is *required*, and if >> yes, what frequency should we input? >> Furthermore, we observed that there is an output for frequency >> synthesizer as well. Can you please indicate in what way one could use it? >> >> We thank you for your patience. >> >> Kind regards, >> Nitish Ragoomundun >> Department of Physics >> University of Mauritius >> >> -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
