Alas, there seems to be no such System Generator FIFO block with different
input output widths. The FIFO block I provide has been used for a few years
now in our beamformers, but assumes a careful user.

On Fri, Apr 26, 2019 at 8:15 PM David MacMahon <dav...@berkeley.edu> wrote:

> I thought that system generator included a FIFO block with different input
> output widths. As I recall, the only tricky parts were ensuring that the
> overall input/output throughputs are commensurate (true for any FIFO,
> really) and, for cases with input 2x wider than output, ensuring that the
> input is “half-word swapped” appropriately so that the output stream is
> properly ordered.
>
> Maybe I’m thinking of the dual port BRAM block that can easily be coerced
> to act as a FIFO?
>
> HTH (despite the lack of actionable details),
> Dave
>
> > On Apr 25, 2019, at 14:28, Jack Hickish <jackhick...@gmail.com> wrote:
> >
> > Hi Indrajit,
> >
> > I'm surprised that the Xilinx FIFO block doesn't give the option of
> > having ports of two different widths. However, if it doesn't, the
> > easiest thing to do might be to use a dual port RAM, which does allow
> > the two interfaces to have different widths. If you can explain a bit
> > more about what you're trying to achieve someone may already have a
> > solution (for example, lots of designs have logic to turn N-bit data
> > streams into 64-bit streams which can be used to feed the 10GbE
> > block).
> >
> > Cheers
> > Jack
> >
> >> On Thu, 25 Apr 2019 at 06:53, Indrajit Barve <indra...@iiap.res.in>
> wrote:
> >>
> >> Hello all,
> >>
> >> I would like to implement a FIFO with input port data type depth and
> width of 2048 X 32 and output port data type 1024 X 64. Basically looking a
> similar module like this
> https://www.xilinx.com/support/documentation/application_notes/xapp261.pdf
> .  or how to implement / configure  Data-Width Conversion for a FIFO on
> ROACH1 .
> >>
> >> Thanks
> >> Indrajit
> >>
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