Dear Javier,

The delay is mostly always in clock cycles. It is assumed your design is
running at some optimum clock frequency, so everything should be referenced
to clock cycles.

BRAM latency = 1) the number of clock cycles taken for the data to be
stored into the RAM after a write signal is asserted or 2) the number of
clock cycles taken for the data to appear at the output of the BRAM after a
read is asserted.

There is often an input register stage and output register stage that add
to this latency. If you are using the BRAM configured as a dual port RAM
then you will mostly likely have a diferent write and read clock. The BRAM
will often need a few clock cycles to synchronise to different clock
domains. The same for a FIFO.

If you want to align a specific data signal (A) with another signal (B)
that is lagging then normally inserting a delay block (with the required
delay in clock cycles) after the specific data signal (A) will work. You
can determine the delays by simulating your design.

I hope this helps.

Kind regards,

Adam Isaacson
South African Radio Astronomy Observatory (SARAO)
Hardware Manager
Cell: (+27) 825639602
Tel:  (+27) 215067300
email: aisaac...@ska.ac.za



On Thu, Oct 17, 2019 at 5:29 PM luis javier Ulloa <ulloa.200921...@gmail.com>
wrote:

> Hello everyone, I hope your support, I am using the Programmable Delay
> block in BRAM, the goal is to delay a signal to put it in phase with
> another, the first question would be, can you serve me for it ?, on the
> other hand, when you talk about delay What do you mean? Will it be clock
> cycles? When talking about BRAM Latency, what do you mean?
> I hope you can guide me with my doubts.
> Regards
> Ulloa
>
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