Hey Luke, I assume you are working on the ADC for the ZCU111, right? If so, the mlib-devel repo has a branch with the AXI Lite interface to the MPSoC and Brian Bradfords forked version of that repo has the beginning workings of adding the interface to the RFDC yellow block that he and I were working on. I have been working on it but things have been slow for me. Mostly because I’m learning hardware and HDL but also I have been doing other architecture work on ALPACA.
So I’d start there. We are close to having it as a yellow block. Perhaps you can help us finish it out? Best, Mitch > On Nov 26, 2019, at 4:56 PM, Luke Hawkins <lhawk...@nrao.edu> wrote: > > Hello All, > > I was wondering if anybody had any tips about adding a yellow block (ADC) > that has and AXI4-Lite interface to a platform design? > > Is it as easy as adding something like (taken from red_pitaya_10.yaml): > mmbus_architecture: AXI4-Lite > mmbus_base_address: 0x40000000 > # How to address each 32-bit (i.e. 4 indicates byte-addressable) > mmbus_address_alignment: 4 > > To the platform file, and something like lines 20-57 from > https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/yellow_blocks/sw_reg.py > to the Yellow Block's py file? > > -LH > > -- > You received this message because you are subscribed to the Google Groups > "casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/7b0579d8cfd23332ece5f06401d325c5.squirrel%40webmail.gb.nrao.edu. -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/E3779F78-6F62-41BE-BF0D-508AA2AD1C47%40byu.edu.
