Hi Wei,
What version of the PYNQ sd card image and vivado is this based on?
-Jeb
——
Dr. J.I. Bailey, III (Jeb) / Project Scientist
Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of Physics, UCSB
jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
> On Oct 7, 2020, at 11:46 AM, Wei Liu <liuwei_berke...@berkeley.edu> wrote:
>
> Hi Colm,
>
> Currently, I put the code in my github, and you can get it here:
> https://github.com/liuweiseu/casper_zcu111.git
>
> Before you use it, you may need to read "Preparations for zcu111.docx" in
> ./preparations_for_zcu111.
>
> We will make it available on the CASPER Github after I finish the 1/10/40 GbE
> Yellow Block.
>
> If you have any questions, please feel free to let me know.
>
> Best,
> Wei
>
> On Wednesday, October 7, 2020 at 9:08:16 AM UTC-7 colmbracken wrote:
> Hi Dan,
>
> That's great news re. the CASPER Yellow Blocks for the ZCU111 ADC.
> Does Wei have a github to share that? Or does he intend to make it available
> on the CASPER Github?
>
> Thanks a million,
> Colm
>
> On Wed, 7 Oct 2020 at 02:59, Dan Werthimer <da...@ssl.berkeley.edu
> <applewebdata://AE01AF03-9BCF-4EFB-82F1-1B28E7446C5A>> wrote:
>
>
> hi jeb,
>
> regarding your ZCU111 RFDC question:
> here's some info that might be helpful from wei liu, cc'ed on this.
> btw, wei liu recently made casper yellow blocks for the ZCU111 ADC's.
> he's now working on ZCU111 yellow blocks for 1, 10, and 100 Gbit ethernet.
>
>
>
> from Wei Liu:
> --------------------
>
> I didn't get the keyError: ‘C_Sysref_Master’ before,
> but I had the board locked up issue before.
>
> what I would suggest is
> (1) check his block design in vivado and confirm the 'phys_addr' and
> 'addr_range' of RFDC core are correct.
> When the 'phys_addr' was incorrect, and I was trying to configure the RFDC
> core, I got my zcu111 locked up.
> (2) make sure the data width of the HPM interface on the MPSOC core is
> 128bits instead of 32bits.
> I'm not sure whether his issue is caused by this setting, but the data width
> should be 128bits.
> All Xilinx IP cores with AXI4 interface have 32bits data width, so I set the
> data width of HPM interface on MPSOC to 32bits,
> but the system can't work until I change the data width to 128bits.
>
> Best,
> Wei
>
>
>
> On Tue, Oct 6, 2020 at 6:12 PM Jeb Bailey <bail...@ucsb.edu
> <applewebdata://AE01AF03-9BCF-4EFB-82F1-1B28E7446C5A>> wrote:
> Hi Lewis,
> While that does get rid of the sysref KeyError, executing
> overlay.usp_rf_data_converter_0 now locks up the whole board and I’m forced
> to power cycle.
>
>
> The contents of ol.ip_dict['usp_rf_data_converter_0’] are (excluding the
> parameters):
> {'addr_range': 262144,
> 'device': <pynq.pl_server.device.XlnkDevice at 0x7f922cd780>,
> 'driver': xrfdc.RFdc,
> 'fullpath': 'usp_rf_data_converter_0',
> 'gpio': {},
> 'interrupts': {'irq': {'controller': 'axi_intc_0',
> 'fullpath': 'usp_rf_data_converter_0/irq',
> 'index': 3}},
> 'mem_id': 's_axi',
> 'parameters': { ...},
> 'phys_addr': 2684878848,
> 'registers': {},
> 'state': None,
> 'type': 'xilinx.com <http://xilinx.com/>:ip:usp_rf_data_converter:2.2'}
>
> I’m guessing you came by some of this based on
> https://discuss.pynq.io/t/zcu111-rfsoc-pynq-support-for-vivado-2019-1-hwh-files/685/4?
>
> <https://discuss.pynq.io/t/zcu111-rfsoc-pynq-support-for-vivado-2019-1-hwh-files/685/4?>
>
>
> Any more ideas? As I understand this the python code is depending on
> libxrfdc.so which, since I’m using the 2.5 board image was the result of
> either a 2018.3 or 2019.1 petalinux tool flow run.
>
> -Jeb
>
>
>
>> On Oct 6, 2020, at 1:42 PM, 'Lewis McLaughlin' via cas...@lists.berkeley.edu
>> <applewebdata://AE01AF03-9BCF-4EFB-82F1-1B28E7446C5A>
>> <cas...@lists.berkeley.edu
>> <applewebdata://AE01AF03-9BCF-4EFB-82F1-1B28E7446C5A>> wrote:
>>
>> Hi Jeb,
>>
>> A workaround you can do is to edit the file
>> "/usr/local/lib/python3.6/dist-packages/xrfdc/config.py" on the board.
>>
>> Comment out lines 46,47,60,90,91. These relate to:
>>
>> _DAC_DDP: FifoEnable, AdderEnable
>>
>> _ADC_DDP: FifoEnable
>>
>> Config: MasterADCTile, MasterDACTile
>>
>> Hopefully that works for your problem!
>>
>> Regards,
>> Lewis.
>>
>> On Tue, 6 Oct 2020, 21:27 Jeb Bailey, <bail...@ucsb.edu
>> <applewebdata://AE01AF03-9BCF-4EFB-82F1-1B28E7446C5A>> wrote:
>> Hi Folks,
>> Has anyone here had any success configuring the RFDC block from python
>> using pynq with a bitstream built in Vivado 2019.2?
>>
>> I’m working with the 2.5 ZCU111 SD image with pynq updated to 2.5.4. By
>> using ignore_version=True with loading the overlay I can get the xrfdc
>> driver loaded, however trying to access the block via attributes (e.g.
>> myoverlay.usp_rf_data_converter_0 raises a KeyError: ‘C_Sysref_Master’).
>>
>> My sinking suspicion is that I need to rebuild the pynq SDimage with the
>> 2019.2 tool flow but I'm getting the impression this is also a bit of a
>> minefield, so if anyone as insight on this process (or with 2020.1) I’d be
>> interested here as well.
>>
>> Cheers and thanks.
>>
>> -Jeb
>>
>> ——
>> Dr. J.I. Bailey, III (Jeb) / Project Scientist
>> Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of Physics,
>> UCSB
>> jebbailey.com <http://jebbailey.com/> / +1 (734) 389-5143
>> <tel:(734)%20389-5143> / skype:spacecolonyone <>
>>
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> Dr Colm Bracken
> Lecturer
> Maynooth University Experimental Physics
>
>
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