Hi Sean, just in case you are in a rush to use this platform.. You could use the Pavel Denim IP-cores (https://github.com/pavel-demin/red-pitaya-notes) which gives you the ADC-DAC interface plus some other blocks, and you always could import a simulink design into vivado following the instruction in this Xilinx video (https://www.youtube.com/watch?v=MN4eCrhPvWk&t).
So in theory you could still use the casper DSP blocks (not the yellow ones), but you need to create the brams and registers by yourself in vivado. The brams are already available as an IP block and the registers could be implemented with axi-gpio IP-block or with a custom axi-lite interface HDL. I actually dont know how to translate the bitmap to the katcp interface, but you should be able to do it. Also like you have access to the addresses of the axi bus you could create a custom C-code to interface with them (Is just memory map the /dev/xdevcfg and read/write to the addresses that you set in vivado). El jueves, 15 de octubre de 2020 a las 13:46:10 UTC-3, semc...@colorado.edu escribió: > > Hello Casperites, > > I was looking at the new Red Pitaya board that has come out recently: > > https://www.redpitaya.com/Catalog/p52/sdrlab-122-16-standard-kit?cat=c102 > > It features wider out-of-the box bandwidth (no front end filtering), a > bigger FPGA, and 16-bit ADCs. Are there any plans to add casper support for > this board? > > Regards, > Sean > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/b7e4c1e0-5c28-4cbe-b6eb-d482c1ef58e0n%40lists.berkeley.edu.
