Hi Jeb,

Sorry, I didn't make it clear before.

The PL registers I mean is AXI4-Lite registers in the PL design.

In casper toolflow, we have a server running on the PS part, which can help
us download bit files and access to the PL registers,
so we don't use pynq.Overlay and pynq.mmio.

I was trying to monitor some signals from vivado hardware manager, so I
downloaded the bit file via JTAG directly,
then I found the server can't access to the PL registers any more until I
downloaded the same bit file via pynq.Overlay.

I think if you use pynq.mmio to configure the registers, you will not have
the same issue as I had before,
because you will use pynq.Overlay first.

Best,
Wei

On Mon, Nov 2, 2020 at 9:00 PM Jeb Bailey <baile...@ucsb.edu> wrote:

> What you mean by PL registers? All the PL IO I’ve done has, at one level
> of abstraction or another, been either using pynq.mmio (most often either
> with direct address offsets, the .array[] attribute of the instance, or the
> auto-generated .register_map attribute. I’ve also loaded in date using an
> AXI master in PL that I configured the address via an AXI-Lite register.
> You can also use the pynq.gpio to control the wires into the PL if you
> enable them.
>
>
> -Jeb
>
> ——
> Dr. J.I. Bailey, III (Jeb) / Project Scientist
> Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of
> Physics, UCSB
> jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
>
> On Nov 2, 2020, at 7:04 PM, Wei Liu <liuwei_berke...@berkeley.edu> wrote:
>
> Hi Jeb,
>
> At the beginning of the test, I had the cpu hanging issue.
> I followed the instructions here, and fixed the issue:
>
> https://discuss.pynq.io/t/problem-with-using-integrated-logic-analyzer-ila-for-debugging-with-pynq/435/4
>
> Then I downloaded the bit file via JTAG, the PS part didn't hang until I
> was trying to read/write PL registers,
> so I think it's not caused by cpu_idle.
>
> Did you try to read/write PL registers after you download the bit file via
> JTAG?
> If so, can you please tell me how you did it?
>
> Thanks!
> Best,
> Wei
>
>
>
> On Mon, Nov 2, 2020 at 6:14 PM Jeb Bailey <baile...@ucsb.edu> wrote:
>
>> Hi Wei,
>>    Is there any chance this workaround is related to needing cpu.idle=1
>> on your kernel command line? I know trying to use the system ilas will
>> cause the PS side to hang without it.
>>
>> -Jeb
>>
>> Sent from my mobile.
>>
>> On Nov 2, 2020, at 15:57, Wei Liu <liuwei_berke...@berkeley.edu> wrote:
>>
>> 
>> Hi Casperites,
>>
>> I'm working on porting casper toolflow on ZCU111.
>> I want to share some debugging experiences, which may be helpful.
>>
>> We have PYNQ image running on the PS part, which is based on Ubuntu18.04.
>>
>> I found PL registers can't be accessed after the bit file is downloaded
>> via JTAG.
>> Because PYNQ image is running, SDK can't be used for debugging and no elf
>> file is associated,
>> which causes some initialization unfinished.
>>
>> What I did is download the bit file via JTAG first, so we have the GUI
>> for debugging.
>> Then I downloaded the same bit file via Overlay class from PYNQ, which
>> can finish the necessary initialization.
>> After that, I can monitor signals from the vivado hardware manager, and I
>> can also read or write PL registers.
>>
>> Hope this will be helpful for debugging on MPSOC with PYNQ image.
>>
>> Best,
>> Wei
>>
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