Hi, Heystek,

The CPU/KATCP/CasperFpga data path to the "Shared BRAM" is 32 bits wide, so in 
the end you will be writing/sending an array of 32 bit integers.  The data path 
on the FPGA side of the "shared BRAM" may be wider (e.g. 64 bits) or narrower 
(e.g  8 or 16 bits) or the same (i.e. 32 bits).  Thing are most straightforward 
when the FPGA data path is 32 bits since location 0 is the same for either 
side, but one important detail is that the values in the Shared BRAM are stored 
in "big endian" format (aka "network byte order"), which is opposite from the 
x86_64 convention.  When the widths differ between the two sides, some care is 
required to ensure that the data is ordered properly to get the desired output 
order.  The "Block RAM Address Mapping" section of UG363 
(https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug363.pdf
 
<https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug363.pdf>)
 describes this mapping.  The one detail that is not covered there is when the 
FPGA data port is 64 bits wide.  In that case, you need to convert the 64-bit 
value to big endian, but then swap the low 32-bits and high-32 bits, though 
sometimes the gateware designer will be "clever" and do this swap for you 
(which is convenient if you know about it).

Hope this helps,
Dave

> On Oct 19, 2021, at 12:55, Heystek Grobler <heystekgrob...@gmail.com> wrote:
> 
> Good day everyone. 
> 
> I was hoping that someone can perhaps help me or can point me in the right 
> direction. 
> 
> I want to write sine and cosine waves to BRAM blocks in order to implement a 
> local oscillator. I have a basic idea of how to do this by making use of a 
> struct that needs to be packed, but in practice I have not done this before 
> and can't seem to find a good example to follow. 
> 
> Thank you for the help! 
> 
> Heystek 
> 
> 
>  
> 
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