*board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)* *.* [image: smlexternal_PPS.png] The above shows an external PPS driving an ADC that is SPI's into the XCZU48DR. In what manner would the FPGA fabric access these pins in a design? Should the PLLs be programmed externally to align with this input?
I have not seen any of these names re-occurring in say Xilinx document pg269, nor in Zynq document ug1085 (the full tech ref manual). How could these pins be accessed? Has anyone had luck in accessing the 1PPS SMA there, say for connecting to an external GPSDO? Thank you. -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/969d90a1-5bca-4325-8718-f9b4e53838f9n%40lists.berkeley.edu.
