Hi Yunfan,

Could you please try the `m2021a-dev` 
<https://github.com/casper-astro/mlib_devel/tree/m2021a-dev> branch of 
`mlib_devel` and see if it helps resolve your issues with setting up the clock 
configuration?

This development branch has new changes and adjustments that make simpler and 
straightforward in setting up the tile clocking sources. For the 4x2 board 
specifically, you should no longer need to make any adjustments under the 
“System Clocking” tab and it will be correct for the enabled ADC/DAC tiles you 
choose to use in your design.

Hope this helps,
Mitch

> On Feb 20, 2024, at 12:39 PM, Yunfan Zhang <yunfan.zha...@duke.edu> wrote:
> 
> Dear CASPER Team,
>  
> I really thanked for helping to solve the connection problem to the RFSoC4*2 
> Board for me. Now I have encounter problem using the RFDC block. I have 
> followed the tutorial which set the sampling rate to 3932.16 Msps, Clock Out 
> and Reference Clock 245.76 MHz. As the RFSoC 4*2, only tile 224 and tile 226 
> would be used. Thus, I only checked the Tile 224, 225 and 226 only. From the 
> datasheet of the chip, I have set the clock source to ADC tile 1 (tile 225) 
> and Tile 0, Tile 2 are both tiled to 225. Which shown like the following 
> figures:
>  
> <image001.png>
> <image002.png>
> <image003.png>
> <image004.png>
> <image005.png>
>  
> However, when I check the status of the ADC, it stuck at the State 6, the PLL 
> do not work. Is there any wrong for my configuration? I have also tried the 
> configuration as same as the Tutorial 2, but also stuck at state 7, which PLL 
> do not works.
> <image008.png><image007.png>
>  
> I have also tried that the clock source directly connected to the Tile 224 
> and Tile 226 and do not distribute the clock from these two tiles, they both 
> stuck at State 7, with still PLL would not working.
> <image006.png>
>  
> Any possible solution would be great help!
>  
> Best regards,
> Yunfan
> 
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> <Schematic.png><Setting1.png><Setting2.png><Setting3.png><Setting4.png><Setting5.png><Result.png><Result1.png>

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