Dear CASPER Team, I want to know if it is possible to use the DRAM (total 8GB) on RFSoC to store the ADC sampling data. I have tried to switch the 'bitfiled_snapshot' block storage medium to 'DRAM' and it shows the problem that "There is no block name xps_library/dram", when I configured the DRAM clock to 200MHz, dimm is 2. So I think the bitfiled_snapshot could not switch to DRAM for storage data for RFSoC 4*2 board.
Then I found out that there is a 'dram' block in the toolflow. Should I need to use this block to directly store the ADC sampling data? It seems a lot of ports on that block and it may be tough to find how to fully control it. What I want to design is to store all the ADC sampling data into DRAM until it is full, and then fetch all the data afterwards to the computer. Is there any suggestion about achieving this? Any help would be greatly appreciated! Thank you again for the help! Best regards, Yunfan -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/aee3698f-2ceb-4ee2-8230-7e34ebedc8d7n%40lists.berkeley.edu.
