This should be relatively straightforward.
There’s nothing special about the Multi-Gigabit transceivers used on the QSFP28
port. Normally for 100G they use 4 lanes with each lane operating at 25Gbs
(effective, higher due to encoding and error correction, hence the QSFP28).
But the fact is that you can run these at 10Gigabit/sec instead and make the
port a QSFP 40Gbit port, which can then be subdivided to a 10Gbit port using a
breakout cable.
To save power you can then turn off the unused transceivers to get a single
10Gb port in the FPGA, and similarly with serial commands to the Fiberoptic
transceiver the extra lasers can also be turned off if desired. [you don’t have
to worry about that part if your using a direct connect cable].
In the fpga:
* Generate the Ethernet Port for 10Gb as if you were targeting a SFP+ eg
run it in 10Gbase-SR mode.
* This will have the effect of changing the bitwidth going into the
Xilinx IP block to a smaller AXI streaming size which will then trigger
rejiggering of any ethernet packetization logic you might have implementing UDP
or VDIF or VITA49.2 or what have you
* Replace the casper 100G block with this slower version.
* You’ll need to ensure the bitrate going into the Ethernet/Packetization
logic is <= 10Gbit/sec
* Eg low bitwidth quantization and or decimating to a slow enough sample
rate to fit at 10Gbit/sec
>From a hardware perspective you’ll want to acquire one of these breakout
>cables:
*
https://community.fs.com/article/how-to-convert-a-port-from-qsfp-to-sfp-port.html
* (you’ll then just not use 3 out of 4 of the 10G SFP+ connections)
I hope you find someone. I’d love to volunteer, but I have a full time job….
Hopefully you’ll see some 400G progress at the next Casper Conference =c)
[AB72FAB9]
Matthew Schiller
ngVLA Digital Backend Lead
NRAO
mschi...@nrao.edu<mailto:mschi...@nrao.edu>
315-316-2032
From: casper@lists.berkeley.edu <casper@lists.berkeley.edu> On Behalf Of John
Swoboda
Sent: Wednesday, October 2, 2024 11:40 AM
To: casper@lists.berkeley.edu
Subject: [casper] Temp FPGA Development Project {External}
Hi,
MIT Haystack in collaboration with Spectrum X is looking for someone to do temp
work with the RFSoCs. The main goal of the project is to find a way enable a
way to stream data out of 100 Gbe on the RFSoC to a 10 Gbe connection on a host
computer (we would provide remote access to a test bed). The reason for doing
this is we are looking for low power solutions to stream high bandwidth data
from the RFSoC. We are specifically looking at an application with the 4x2 with
the hope that this could be extended to other platforms in the RFSoC family. We
will initially target the Pynq framework to test this capability but are also
interested in extending this to CASPER.
We believe we have the place to start but we need someone with experience using
Vivado and VHDL/Verilog. If you're interested in this task, or know someone who
might be, please contact me.
John Swoboda, Ph.D. (he/him)
Geospace Research Scientist
MIT Haystack Observatory
Email: swo...@mit.edu<mailto:swo...@mit.edu>
Voice: (617) 715-3489
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