Hi Jack,
I was going through the mailing archive wherein I saw a mail by Kaj Wiik
mentioning "Vivado fails when using capital letters in Simulink project
names (sort of solved)".
So, I renamed the slx file and the previously shared error got resolved and
the following error was encountered instead:
*** Running vivado
with args -log top.vds -m64 -product Vivado -mode batch -messageDb
vivado.pb -notrace -source top.tcl
****** Vivado v2021.1.1 (64-bit)
**** SW Build 3286242 on Wed Jul 28 13:09:46 MDT 2021
**** IP Build 3279568 on Wed Jul 28 16:48:48 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source top.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository
'/home/casper-ubuntu20/Desktop/CASPER/temp/Sangee/redpitaya_led_v1/sysgen'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/home/casper-ubuntu20/tools/Xilinx/Vivado/2021.1/data/ip'.
Command: synth_design -top top -part xc7z010clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device
'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a
maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado
processes
INFO: [Synth 8-7075] Helper process launched with PID 58261
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 .
Memory (MB): peak = 2488.039 ; gain = 0.000 ; free physical = 113785 ; free
virtual = 121711
---------------------------------------------------------------------------------
ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a
string literal
[/home/casper-ubuntu20/Desktop/CASPER/temp/Sangee/redpitaya_led_v1/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:94]
ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a
string literal
[/home/casper-ubuntu20/Desktop/CASPER/temp/Sangee/redpitaya_led_v1/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:95]
INFO: [Synth 8-2810] unit axi4lite_axi4lite_top_mmap_pkg ignored due to
previous errors
[/home/casper-ubuntu20/Desktop/CASPER/temp/Sangee/redpitaya_led_v1/myproj/myproj.srcs/sources_1/imports/xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:67]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 .
Memory (MB): peak = 2488.039 ; gain = 0.000 ; free physical = 113353 ; free
virtual = 121279
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Sat Jan 10 10:29:49 2026...
[Sat Jan 10 10:29:59 2026] synth_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'synth_1'
wait_on_run: Time (s): cpu = 00:02:51 ; elapsed = 00:01:14 . Memory (MB):
peak = 2670.289 ; gain = 0.000 ; free physical = 114488 ; free virtual =
122414
# open_run synth_1
ERROR: [Common 17-69] Command failed: Run 'synth_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Sat Jan 10 10:29:59 2026...
Traceback (most recent call last):
File
"/home/casper-ubuntu20/Desktop/CASPER/mlib_devel/jasper_library/exec_flow.py",
line 239, in <module>
backend.compile(cores=opts.jobs, plat=platform,
File
"/home/casper-ubuntu20/Desktop/CASPER/mlib_devel/jasper_library/toolflow.py",
line 2329, in compile
raise Exception('Vivado failed!')
Exception: Vivado failed!
Error using jasper (line 23)
Backend build failed! Check log files for more information
Thanks for the help in advance.
Regards,
Sangeetha
On Sat, 10 Jan 2026 at 10:14, Sangeetha Andavan <[email protected]>
wrote:
> Hi Jack,
>
> Actually you are right, towards the end I am seeing the following error:
>
> ERROR: [Coretcl 2-1134] No IP matching VLNV
> 'User_Company:SysGen:RedPitaya_led_v1:1.0' was found. Please check your
> repository configuration.
> INFO: [Common 17-206] Exiting Vivado at Fri Jan 9 18:55:37 2026...
> Traceback (most recent call last):
> File
> "/home/casper-ubuntu20/Desktop/CASPER/mlib_devel/jasper_library/exec_flow.py",
> line 239, in <module>
> backend.compile(cores=opts.jobs, plat=platform,
> File
> "/home/casper-ubuntu20/Desktop/CASPER/mlib_devel/jasper_library/toolflow.py",
> line 2329, in compile
> raise Exception('Vivado failed!')
> Exception: Vivado failed!
> Error using jasper (line 23)
> Backend build failed! Check log files for more information
>
> Moreover, I am attaching log files for your kind reference.
> Thanks in advance for your help.
>
> Regards,
> Sangeetha
>
> On Fri, 9 Jan 2026 at 18:53, Jack Hickish <[email protected]> wrote:
>
>> Hi Sangeetha,
>>
>> The text you pasted is some tcl which sets up functions to print warnings
>> in the event of timing errors.
>> You'll always see this code fly by, since the tcl input is printed to
>> screen.
>>
>> If you actually have timing errors you will see, towards the end of your
>> build:
>>
>> ERROR: Found timing violations => Worst Setup Slack: <some negative
>> number> ns
>> ERROR: Found timing violations => Total Setup Slack: <some other negative
>> number> ns
>>
>> Do you see these?
>>
>> Cheers
>> Jack
>>
>> On Fri, 9 Jan 2026 at 13:04, Sangeetha Andavan <[email protected]>
>> wrote:
>>
>>> Hi everyone,
>>>
>>> I’m Sangeetha, new to CASPER. I’m currently learning how to use the
>>> CASPER toolflow to design simple digital backends, starting with older
>>> platforms such as RedPitaya, SKARAB, and SNAP.
>>>
>>> While following the tutorial for a basic LED blinking design, I
>>> encountered a timing-related error during the build. The relevant debug
>>> output is shown below:
>>>
>>> [2026-01-09
>>> 17:37:17,207][toolflow.py:1927][add_tcl_cmd][DEBUG][MainThread]: Adding tcl
>>> command:
>>>
>>> proc check_timing {run} {
>>> if { [get_property STATS.WNS [get_runs $run] ] < 0 } {
>>> send_msg_id "CASPER-1" {CRITICAL WARNING} "ERROR: Found timing
>>> violations => Worst Negative Slack: [get_property STATS.WNS [get_runs
>>> $run]] ns"
>>> } else {
>>> puts "No timing violations => Worst Negative Slack: [get_property
>>> STATS.WNS [get_runs $run]] ns"
>>> }
>>>
>>> if { [get_property STATS.TNS [get_runs $run] ] < 0 } {
>>> send_msg_id "CASPER-1" {CRITICAL WARNING} "ERROR: Found timing
>>> violations => Total Negative Slack: [get_property STATS.TNS [get_runs
>>> $run]] ns"
>>> }
>>>
>>> if { [get_property STATS.WHS [get_runs $run] ] < 0 } {
>>> send_msg_id "CASPER-1" {CRITICAL WARNING} "ERROR: Found timing
>>> violations => Worst Hold Slack: [get_property STATS.WHS [get_runs $run]] ns"
>>> } else {
>>> puts "No timing violations => Worst Hold Slack: [get_property STATS.WHS
>>> [get_runs $run]] ns"
>>> }
>>>
>>> if { [get_property STATS.THS [get_runs $run] ] < 0 } {
>>> send_msg_id "CASPER-1" {CRITICAL WARNING} "ERROR: Found timing
>>> violations => Total Hold Slack: [get_property STATS.THS [get_runs $run]] ns"
>>> }
>>> }
>>>
>>> Based on my understanding, I checked the platform clock settings and set
>>> the clock frequency to 125 MHz, corresponding to the ADC clock. However,
>>> the timing violation persists.
>>>
>>> I would really appreciate any guidance on whether the clock
>>> configuration is correct for this tutorial, or if I’m missing something
>>> fundamental in the setup.
>>>
>>> Thanks in advance for your help.
>>>
>>> Best regards,
>>> Sangeetha
>>>
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>>>
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>>
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