>>>> ----- Original Message ----- From: "Dave G4UGM" <dave.g4...@gmail.com> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk@classiccmp.org> Sent: Tuesday, 14 July, 2015 8:58:09 AM Subject: RE: Reproducing old machines with newer technology (Re: PDP-12 at the RICM) ... My next project is likely to be the Ferranti Pegasus which is several orders of magnitude more complex than the Baby and will need a proper plan. <<<<
"There may be troubles ahead" … I had plans for doing something similar for the ICT1905 (FP6000) and discovered two catches in translating the logic diagrams: FPGAs are designed around the modern concept of a single clock that is widely distributed and having flipflop control by gating the input signals whereas early Ferranti machines (1900, at least pre "A" series, Atlas*, and presumably Pegasus) used "strobes" which are hard and inefficient to do in a FPGA. Maybe less likely to be the case in the Pegasus is the widespread use of "wired-or" which can be hard to recognise in the logic diagrams (and, again, requires translating into "real" gates in an FPGA) Obviously a register transfer model wouldn't have those problems compared to a gate-level model and would be considerably simpler to implement but then risks losing some of the (possibly undocumented) edge cases. * Atlas would, presumably, be even trickier due to the use of asynchronous logic. Good luck, should be an "interesting" exercise. Andy
