On 11/23/2015 07:05 PM, Paul Koning wrote: > Then again, multiplying by a constant is trivial, and in a modern HDL you > just write the expression you need. The synthesis will construct some adds > and shifts out of that. In fact, even if you want to supply the geometry > values from a table (so you're multiplying by variable values) that's no big > deal; two multipliers won't make a dent in any modern FPGA.
That's why that's my first choice. I just don't think it will be a problem. > Sure, you can throw in a microcontroller, but interfacing that is likely to > take far more gates than doing the mapping in the device directly. The original reason for the microcontroller is to implement the USB protocol. I didn't feel up to that in Verilog.
